From 2e6bc2b257d7d3035ef6ac688eaeb5f25ca7b549 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Oct 2022 20:42:17 +0100
Subject: [PATCH] add 8-bit elwidth alu svp64 case

---
 .../decoder/isa/test_caller_svp64_elwidth.py  | 26 +++++++++++++++++
 src/openpower/test/alu/svp64_cases.py         | 29 +++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 src/openpower/decoder/isa/test_caller_svp64_elwidth.py

diff --git a/src/openpower/decoder/isa/test_caller_svp64_elwidth.py b/src/openpower/decoder/isa/test_caller_svp64_elwidth.py
new file mode 100644
index 00000000..4f6a8727
--- /dev/null
+++ b/src/openpower/decoder/isa/test_caller_svp64_elwidth.py
@@ -0,0 +1,26 @@
+""" Decoder tests
+
+related bugs:
+
+ *
+"""
+
+import unittest
+from openpower.test.runner import TestRunnerBase
+from openpower.test.alu.svp64_cases import SVP64ALUElwidthTestCase
+
+# writing the test_caller invocation this way makes it work with pytest
+
+
+class TestSVP64ALU(TestRunnerBase):
+    def __init__(self, test):
+        assert test == 'test'
+        super().__init__(SVP64ALUElwidthTestCase().test_data)
+
+    def test(self):
+        # dummy function to make unittest try to test this class
+        pass
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/src/openpower/test/alu/svp64_cases.py b/src/openpower/test/alu/svp64_cases.py
index 25d515a8..86ad4be1 100644
--- a/src/openpower/test/alu/svp64_cases.py
+++ b/src/openpower/test/alu/svp64_cases.py
@@ -3,6 +3,35 @@ from openpower.endian import bigendian
 from openpower.simulator.program import Program
 from openpower.decoder.isa.caller import SVP64State, CRFields
 from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.test.state import ExpectedState
+from copy import deepcopy
+
+class SVP64ALUElwidthTestCase(TestAccumulatorBase):
+
+    def case_1_sv_add_ew8(self):
+        """>>> lst = ['sv.add/ew=8 *1, *5, *9']
+        """
+        isa = SVP64Asm(['sv.add *1, *5, *9'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[9] = 0x1220
+        initial_regs[5] = 0x43ff
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl = 2  # VL
+        svstate.maxvl = 2  # MAXVL
+        print("SVSTATE", bin(svstate.asint()))
+
+        # expected: each 8-bit add is completely independent
+        gprs = deepcopy(initial_regs)
+        gprs[1] = 0x551f # 0x12+0x43 = 0x55, 0x20+0xff = 0x1f (8-bit)
+        e = ExpectedState(pc=8, int_regs=gprs)
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate, expected=e)
 
 
 class SVP64ALUTestCase(TestAccumulatorBase):
-- 
2.30.2