From 2e8f0a97d63d24d325a68d54d0b4a1d248f4449d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 13:05:15 +0100 Subject: [PATCH] clarify abridged --- simple_v_extension/abridged_spec.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 981308b6d..8197c17d0 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -37,10 +37,10 @@ the behaviour becomes effectively identical to standard RV execution, however SV is never truly actually "off". Note: **there are *no* new opcodes**. The scheme works *entirely* -on hidden context that augments *scalar* RISC-V instructions. Thus it -may cover existing, future and custom scalar extensions, turning all -existing, all future and all custom scalar operations parallel, without -requiring any special opcodes to do so. +on hidden context that augments (nests) *scalar* RISC-V instructions. +Thus it may cover existing, future and custom scalar extensions, turning +all existing, all future and all custom scalar operations parallel, +without requiring any special (identical, parallel variant) opcodes to do so. # CSRs -- 2.30.2