From 2e92185a033ec94d3dbaf22577110883db1474a1 Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sun, 21 Jul 2019 20:58:54 +0000 Subject: [PATCH] or1k: Fix code quality for volatile memory loads Volatile memory does not match the memory_operand predicate. This causes extra extend/mask instructions instructions when reading from volatile memory. On OpenRISC loading volatile memory can be treated the same as regular memory loads which supports combined sign/zero extends. Fixing this eliminates the need for extra extend/mask instructions. This also adds a test provided by Richard Selvaggi which uncovered the issue while we were looking into another issue. gcc/ChangeLog: PR target/90363 * config/or1k/or1k.md (zero_extendsi2): Update predicate. (extendsi2): Update predicate. * gcc/config/or1k/predicates.md (volatile_mem_operand): New. (reg_or_mem_operand): New. gcc/testsuite/ChangeLog: PR target/90363 * gcc.target/or1k/swap-1.c: New test. * gcc.target/or1k/swap-2.c: New test. From-SVN: r273647 --- gcc/ChangeLog | 8 ++++++++ gcc/config/or1k/or1k.md | 6 +++--- gcc/config/or1k/predicates.md | 18 ++++++++++++++++++ gcc/testsuite/ChangeLog | 6 ++++++ 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7f070e87f27..59e11bccfbd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-07-22 Stafford Horne + + PR target/90363 + * config/or1k/or1k.md (zero_extendsi2): Update predicate. + (extendsi2): Update predicate. + * gcc/config/or1k/predicates.md (volatile_mem_operand): New. + (reg_or_mem_operand): New. + 2019-07-21 Iain Sandoe * config/rs6000/rs6000.c (TARGET_NO_PROTOTYPE): Move from here... diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 2dad51cd46b..757d899c442 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -328,11 +328,11 @@ ;; Sign Extending ;; ------------------------------------------------------------------------- -;; Zero extension can always be done with AND and an extending load. +;; Zero extension can always be done with AND or an extending load. (define_insn "zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "" "@ l.andi\t%0, %1, @@ -344,7 +344,7 @@ (define_insn "extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "TARGET_SEXT" "@ l.exts\t%0, %1 diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index 879236bca49..dad1c5d4be3 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -82,3 +82,21 @@ (define_predicate "equality_comparison_operator" (match_code "ne,eq")) + +;; Borrowed from rs6000 +;; Return true if the operand is in volatile memory. Note that during the +;; RTL generation phase, memory_operand does not return TRUE for volatile +;; memory references. So this function allows us to recognize volatile +;; references where it's safe. +(define_predicate "volatile_mem_operand" + (and (match_code "mem") + (match_test "MEM_VOLATILE_P (op)") + (if_then_else (match_test "reload_completed") + (match_operand 0 "memory_operand") + (match_test "memory_address_p (mode, XEXP (op, 0))")))) + +;; Return true if the operand is a register or memory; including volatile +;; memory. +(define_predicate "reg_or_mem_operand" + (ior (match_operand 0 "nonimmediate_operand") + (match_operand 0 "volatile_mem_operand"))) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fc9b4c8d24f..95e73d9fa48 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2019-07-22 Stafford Horne + + PR target/90363 + * gcc.target/or1k/swap-1.c: New test. + * gcc.target/or1k/swap-2.c: New test. + 2019-07-20 Segher Boessenkool * gcc.target/powerpc/volatile-mem.c: New testcase. -- 2.30.2