From 2e9e745efa03363f9f0d5cc47696401d55a8e5d2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 09:26:08 -0700
Subject: [PATCH] Do not simplemap for variable test

---
 tests/xilinx/xilinx_srl.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys
index 4e3c44a98..b8df0e55a 100644
--- a/tests/xilinx/xilinx_srl.ys
+++ b/tests/xilinx/xilinx_srl.ys
@@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test
 prep
 design -save gold
 
-simplemap t:$dff t:$dffe
 xilinx_srl -variable
 opt
 
 #stat
 # show -width
 # write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 t:$dff
+select -assert-count 1 t:$dff r:WIDTH=1 %i
 select -assert-count 2 t:$__XILINX_SHREG_
 
 design -stash gate
-- 
2.30.2