From 2eca87fd3e9327c584d1dcb943a08cb805379162 Mon Sep 17 00:00:00 2001 From: "Samuel A. Falvo II" Date: Tue, 21 Jul 2020 20:08:32 -0700 Subject: [PATCH] PEP8 compliance --- src/soc/fu/trap/formal/proof_main_stage.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py index d80ab6b6..eef9a658 100644 --- a/src/soc/fu/trap/formal/proof_main_stage.py +++ b/src/soc/fu/trap/formal/proof_main_stage.py @@ -56,8 +56,8 @@ class Driver(Elaboratable): with m.Case(MicrOp.OP_SC): expected_msr = Signal(len(msr_o.data)) comb += expected_msr.eq(op.msr) - # Unless otherwise documented, these exceptions to the MSR bits are - # documented in Power ISA V3.0B, page 1063 or 1064. + # Unless otherwise documented, these exceptions to the MSR bits + # are documented in Power ISA V3.0B, page 1063 or 1064. comb += expected_msr[MSR.IR].eq(0) comb += expected_msr[MSR.DR].eq(0) comb += expected_msr[MSR.FE0].eq(0) @@ -78,7 +78,9 @@ class Driver(Elaboratable): with m.If(op.msr[MSR.TSs:MSR.TSe+1] == 0b10): comb += expected_msr[MSR.TSs:MSR.TSe+1].eq(0b01) with m.Else(): - comb += expected_msr[MSR.TSs:MSR.TSe+1].eq(op.msr[MSR.TSs:MSR.TSe+1]) + comb += expected_msr[MSR.TSs:MSR.TSe+1].eq( + op.msr[MSR.TSs:MSR.TSe+1] + ) # Power ISA V3.0B, Book 2, Section 3.3.1 with m.If(field(op.insn, 20, 26) == 1): -- 2.30.2