From 2efcf8792557e4a71eb195c8793abbc25d5463d1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 May 2020 14:09:05 +0200 Subject: [PATCH] targets/nexys4ddr: update add_sdcard method. Tested with: sdinit sdtestwrite 0x10 foobar sdtestread 0x10 --- litex/boards/targets/nexys4ddr.py | 48 ++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index decaf738..5875af81 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -25,7 +25,9 @@ from litesdcard.phy import SDPHY from litesdcard.clocker import SDClockerS7 from litesdcard.core import SDCore from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker +from litesdcard.data import SDDataReader, SDDataWriter from litex.soc.cores.timer import Timer +from litex.soc.interconnect import wishbone # CRG ---------------------------------------------------------------------------------------------- @@ -53,6 +55,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): + mem_map = {**SoCCore.mem_map, **{ + "sdread": 0x80002000, # len: 0x200 + "sdwrite": 0x80002200, # len: 0x200 + }} def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = nexys4ddr.Platform() @@ -93,27 +99,49 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq) self.add_csr("leds") - def add_sdcard(self): + def add_sdcard(self, memory_size=512, memory_width=32): sdcard_pads = self.platform.request("sdcard") if hasattr(sdcard_pads, "rst"): self.comb += sdcard_pads.rst.eq(0) self.submodules.sdclk = SDClockerS7(sys_clk_freq=self.sys_clk_freq) self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device) - self.submodules.sdcore = SDCore(self.sdphy) + self.submodules.sdcore = SDCore(self.sdphy, csr_data_width=self.csr_data_width) self.submodules.sdtimer = Timer() self.add_csr("sdclk") self.add_csr("sdphy") self.add_csr("sdcore") self.add_csr("sdtimer") - self.submodules.bist_generator = BISTBlockGenerator(random=True) - self.submodules.bist_checker = BISTBlockChecker(random=True) - self.add_csr("bist_generator") - self.add_csr("bist_checker") - self.comb += [ - self.sdcore.source.connect(self.bist_checker.sink), - self.bist_generator.source.connect(self.sdcore.sink) - ] + # SD Card data reader + + sdread_mem = Memory(memory_width, memory_size//4) + sdread_sram = FullMemoryWE()(wishbone.SRAM(sdread_mem, read_only=True)) + self.submodules += sdread_sram + + self.add_wb_slave(self.mem_map["sdread"], sdread_sram.bus, memory_size) + self.add_memory_region("sdread", self.mem_map["sdread"], memory_size) + + sdread_port = sdread_sram.mem.get_port(write_capable=True); + self.specials += sdread_port + self.submodules.sddatareader = SDDataReader(port=sdread_port, endianness=self.cpu.endianness) + self.add_csr("sddatareader") + self.comb += self.sdcore.source.connect(self.sddatareader.sink), + + # SD Card data writer + + sdwrite_mem = Memory(memory_width, memory_size//4) + sdwrite_sram = FullMemoryWE()(wishbone.SRAM(sdwrite_mem, read_only=False)) + self.submodules += sdwrite_sram + + self.add_wb_slave(self.mem_map["sdwrite"], sdwrite_sram.bus, memory_size) + self.add_memory_region("sdwrite", self.mem_map["sdwrite"], memory_size) + + sdwrite_port = sdwrite_sram.mem.get_port(write_capable=False, async_read=True, mode=READ_FIRST); + self.specials += sdwrite_port + self.submodules.sddatawriter = SDDataWriter(port=sdwrite_port, endianness=self.cpu.endianness) + self.add_csr("sddatawriter") + self.comb += self.sddatawriter.source.connect(self.sdcore.sink), + self.platform.add_period_constraint(self.sdclk.cd_sd.clk, period_ns(self.sys_clk_freq)) self.platform.add_period_constraint(self.sdclk.cd_sd_fb.clk, period_ns(self.sys_clk_freq)) self.platform.add_false_path_constraints( -- 2.30.2