From 2f499e805e4401a75a79e41506af8b3a4f50b05b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 12:09:14 +0100 Subject: [PATCH] clarify C.MV VMERGE --- simple_v_extension/abridged_spec.mdwn | 4 ++-- simple_v_extension/specification.mdwn | 7 +++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 22310985c..30f147d61 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -624,8 +624,8 @@ vector | vector | src == dest | sparse VCOPY | """]] Also, VMERGE may be implemented as back-to-back (macro-op fused) C.MV -operations with inversion on the src and dest predication for one of the -two C.MV operations. +operations with zeroing off, and inversion on the src and dest +predication for one of the two C.MV operations. ### FMV, FNEG and FABS Instructions diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 84d5f5fca..7d929c907 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1375,8 +1375,11 @@ vector | vector | src == dest | sparse VCOPY | """]] Also, VMERGE may be implemented as back-to-back (macro-op fused) C.MV -operations with inversion on the src and dest predication for one of the -two C.MV operations. +operations with zeroing off, and inversion on the src and dest predication +for one of the two C.MV operations. The non-inverted C.MV will place +one set of registers into the destination, and the inverted one the other +set. With predicate-inversion, copying and inversion of the predicate mask +need not be done as a separate (scalar) instruction. Note that in the instance where the Compressed Extension is not implemented, MV may be used, but that is a pseudo-operation mapping to addi rd, x0, rs. -- 2.30.2