From 2f4e5800cb6ef8d39ed58dfd448381f82bfb3404 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Date: Sat, 14 Mar 2020 10:31:57 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of
 standards

---
 50/5fe34e8afd443c64dff1ef08165bf5ac421b84 | 65 +++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 50/5fe34e8afd443c64dff1ef08165bf5ac421b84

diff --git a/50/5fe34e8afd443c64dff1ef08165bf5ac421b84 b/50/5fe34e8afd443c64dff1ef08165bf5ac421b84
new file mode 100644
index 0000000..1eddce9
--- /dev/null
+++ b/50/5fe34e8afd443c64dff1ef08165bf5ac421b84
@@ -0,0 +1,65 @@
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+Date: Sat, 14 Mar 2020 10:31:57 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
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+Message-ID: <bug-241-13-rYZczaKmCp@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of
+ standards
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-- 
2.30.2