From 2f4e975d447eb4d9872a65f08b81bed7066be700 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 7 Jul 2020 10:46:34 +0100 Subject: [PATCH] dev-arm: Use getIntConfig when reading/writing GICD_ICFGR This patch is changing the getIntConfig helper (which has been used so far by isLevelSensitive only) to make it usable by the read/writes of the GICD_ICFGR register. While the helper was previously returning the irq config bits provided a single irq as an input, this new version is returning the entire GICD_ICFGR word (read/writable) JIRA: https://gem5.atlassian.net/browse/GEM5-667 Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31055 Reviewed-by: Hsuan Hsu Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/dev/arm/gic_v2.cc | 10 +++------- src/dev/arm/gic_v2.hh | 22 ++++++++++++---------- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc index 321337937..302da2f26 100644 --- a/src/dev/arm/gic_v2.cc +++ b/src/dev/arm/gic_v2.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2013, 2015-2018 ARM Limited + * Copyright (c) 2010, 2013, 2015-2018, 2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -250,10 +250,7 @@ GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) if (GICD_ICFGR.contains(daddr)) { uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2; - assert(ix < 64); - /** @todo software generated interrupts and PPIs - * can't be configured in some ways */ - return intConfig[ix]; + return getIntConfig(ctx, ix); } switch(daddr) { @@ -521,8 +518,7 @@ GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data, if (GICD_ICFGR.contains(daddr)) { uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2; - assert(ix < INT_BITS_MAX*2); - intConfig[ix] = data; + getIntConfig(ctx, ix) = data; if (data & NN_CONFIG_MASK) warn("GIC N:N mode selected and not supported at this time\n"); return; diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh index 40a95539c..aefa938cb 100644 --- a/src/dev/arm/gic_v2.hh +++ b/src/dev/arm/gic_v2.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2013, 2015-2019 ARM Limited + * Copyright (c) 2010, 2013, 2015-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -286,13 +286,13 @@ class GicV2 : public BaseGic, public BaseGicRegisters uint32_t intConfig[INT_BITS_MAX*2]; /** GICD_ICFGRn - * get 2 bit config associated to an interrupt. + * @param ctx context id (PE specific) + * @param ix interrupt word index + * @returns the interrupt config word */ - uint8_t getIntConfig(ContextID ctx, uint32_t ix) { - assert(ix < INT_LINES_MAX); - const uint8_t cfg_low = intNumToBit(ix * 2); - const uint8_t cfg_hi = cfg_low + 1; - return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low); + uint32_t& getIntConfig(ContextID ctx, uint32_t ix) { + assert(ix < INT_BITS_MAX*2); + return intConfig[ix]; } /** GICD_ITARGETSR{8..255} @@ -323,11 +323,13 @@ class GicV2 : public BaseGic, public BaseGicRegisters } } - bool isLevelSensitive(ContextID ctx, uint32_t ix) { - if (ix == SPURIOUS_INT) { + bool isLevelSensitive(ContextID ctx, uint32_t int_num) { + if (int_num == SPURIOUS_INT) { return false; } else { - return bits(getIntConfig(ctx, ix), 1) == 0; + const auto ix = intNumToWord(int_num * 2); + const uint8_t cfg_hi = intNumToBit(int_num * 2) + 1; + return bits(getIntConfig(ctx, ix), cfg_hi) == 0; } } -- 2.30.2