From 2f657565934ad805ef87590de3ad93f0988e85e9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 12 Dec 2018 00:05:17 +0000 Subject: [PATCH] add reg workloads --- 3d_gpu/microarchitecture.mdwn | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 4d10af8a3..ac3ba3590 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -433,6 +433,31 @@ ok,so continuing some thoughts-in-order notes:   - FUs therefore only really express the register, memory, and execution     dependencies: they don't actually do the execution. +## Register file workloads + +Note: Vectorisation also includes predication, which is one extra integer read + +Integer workloads: + +* 43% Integer +* 21% Load +* 12% store +* 24% branch + +* 100% of the instruction stream can be integer instructions +* 75% utilize two source operand registers. +* 50% of the instruction stream can be Load instructions +* 25% can be store instructions, +* 25% can be branch instructions + +FP workloads: + +* 30% Integer +* 25% Load +* 10% Store +* 13% Multiplication +* 17% Addition +* 5% branch # References -- 2.30.2