From 2f69f607e3718da685a12e7060055a88e0a151b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Feb 2020 18:16:38 +0100 Subject: [PATCH] integration/soc: fix refactoring issues --- litex/soc/integration/soc.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index e4c36ae9..434ed36a 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -22,6 +22,7 @@ from litex.soc.interconnect import axi from litedram.core import LiteDRAMCore from litedram.frontend.wishbone import LiteDRAMWishbone2Native +from litedram.frontend.axi import LiteDRAMAXI2Native # TODO: # - replace raise with exit on logging error. @@ -607,6 +608,7 @@ class SoCController(Module, AutoCSR): # SoC ---------------------------------------------------------------------------------------------- class SoC(Module): + mem_map = {} def __init__(self, platform, sys_clk_freq, bus_standard = "wishbone", @@ -752,7 +754,7 @@ class SoC(Module): self.cpu.set_reset_address(reset_address) for n, cpu_bus in enumerate(self.cpu.buses): self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus) - self.add_csr("cpu", use_loc_if_exists=True) + self.csr.add("cpu", use_loc_if_exists=True) for name, loc in self.cpu.interrupts.items(): self.irq.add(name, loc) if hasattr(self, "ctrl"): -- 2.30.2