From 2f7bd971292db8f64175977cbbccb597a0f14817 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Sun, 6 Oct 2019 10:47:28 +0200 Subject: [PATCH] fix comments --- litex/soc/cores/icap.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py index 61e8357c..35ef4e36 100644 --- a/litex/soc/cores/icap.py +++ b/litex/soc/cores/icap.py @@ -31,12 +31,12 @@ class ICAP(Module, AutoCSR): self.sync += icap_clk_counter.eq(icap_clk_counter + 1) self.sync += self.cd_icap.clk.eq(icap_clk_counter[3]) - # Resychronize send pulse to icap domain --------------------------------------------------- + # Resynchronize send pulse to icap domain --------------------------------------------------- ps_send = PulseSynchronizer("sys", "icap") self.submodules += ps_send self.comb += [ps_send.i.eq(self.send.re)] - # Generate icap bitstream write sequenceenerate icap bitstream write sequence + # Generate icap bitstream write sequence _csib = Signal(reset=1) _i = Signal(32) _addr = self.addr.storage << 13 -- 2.30.2