From 2f9891616d1a251bbb83b1ab29da7040258847ab Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sun, 19 Jun 2022 14:47:48 -0700
Subject: [PATCH] fix minu[.] to be unsigned

---
 openpower/isa/av.mdwn                   | 4 ++--
 src/openpower/test/bitmanip/av_cases.py | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index fd5424c8..91ef617d 100644
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -59,8 +59,8 @@ X-Form
 
 Pseudo-code:
 
-    if   (RA) < (RB) then RT <- (RA)
-    else                  RT <- (RB)
+    if   (RA) <u (RB) then RT <- (RA)
+    else                   RT <- (RB)
 
 Special Registers Altered:
 
diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index 6e689e9f..a77b5202 100644
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -165,8 +165,8 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 1
         e.intregs[2] = 0x8000_0000_0000_0000
-        e.intregs[3] = 0x8000_0000_0000_0000
-        e.crregs[0] = 0x8 # RT is -ve
+        e.intregs[3] = min(e.intregs[1], e.intregs[2])
+        e.crregs[0] = 0x4
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_avgadd(self):
-- 
2.30.2