From 2fa28c1b5da51e80430949292a9c1c8238301747 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 22 Feb 2015 13:43:29 +0100
Subject: [PATCH] mac: add padding

---
 liteeth/mac/core/__init__.py | 11 ++++++++-
 liteeth/mac/core/padding.py  | 47 ++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100644 liteeth/mac/core/padding.py

diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index d5bf2f93..34a21ad1 100644
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -1,6 +1,6 @@
 from liteeth.common import *
 from liteeth.generic import *
-from liteeth.mac.core import gap, preamble, crc, last_be
+from liteeth.mac.core import gap, preamble, crc, padding, last_be
 
 class LiteEthMACCore(Module, AutoCSR):
 	def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
@@ -37,6 +37,15 @@ class LiteEthMACCore(Module, AutoCSR):
 			tx_pipeline += [preamble_inserter, crc32_inserter]
 			rx_pipeline += [preamble_checker, crc32_checker]
 
+		# Padding
+		padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
+		padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
+		self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
+		self.submodules += RenameClockDomains(padding_checker, "eth_rx")
+
+		tx_pipeline += [padding_inserter]
+		rx_pipeline += [padding_checker]
+
 		# Delimiters
 		if dw != 8:
 			tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
diff --git a/liteeth/mac/core/padding.py b/liteeth/mac/core/padding.py
new file mode 100644
index 00000000..12970fe4
--- /dev/null
+++ b/liteeth/mac/core/padding.py
@@ -0,0 +1,47 @@
+from liteeth.common import *
+from liteeth.generic import *
+
+class LiteEthMACPaddingInserter(Module):
+	def __init__(self, dw, packet_min_length):
+		self.sink = sink = Sink(eth_phy_description(dw))
+		self.source = source = Source(eth_phy_description(dw))
+		###
+		packet_min_data = math.ceil(packet_min_length/(dw/8))
+
+		self.submodules.counter = counter = Counter(max=eth_mtu)
+
+		self.submodules.fsm = fsm = FSM(reset_state="COPY")
+		fsm.act("COPY",
+			counter.reset.eq(sink.stb & sink.sop),
+			Record.connect(sink, source),
+			If(sink.stb & sink.ack,
+				counter.ce.eq(1),
+				If(sink.eop,
+					If(counter.value < (packet_min_data-1),
+						source.eop.eq(0),
+						NextState("PADDING")
+					)
+				)
+			)
+		)
+		fsm.act("PADDING",
+			source.stb.eq(1),
+			source.eop.eq(counter.value == (packet_min_data-1)),
+			source.data.eq(0),
+			If(source.ack,
+				counter.ce.eq(1),
+				If(source.eop,
+					NextState("COPY")
+				)
+			)
+		)
+
+class LiteEthMACPaddingChecker(Module):
+	def __init__(self, dw, packet_min_length):
+		self.sink = sink = Sink(eth_phy_description(dw))
+		self.source = source = Source(eth_phy_description(dw))
+		###
+		# XXX see if we should drop the packet when
+		# payload size < minimum ethernet payload size
+		self.comb += Record.connect(sink, source)
+
-- 
2.30.2