From 2fa96dbc8734cb001478a2350b4687dfb19d1e5c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 16:27:11 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 26e9ec854..e47259136 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -208,6 +208,8 @@ Fields: * **sz / dz** if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) +* **CRM** affects the CR on reduce mode when Rc=1 +* **N** sets signed/unsigned saturation. ## Notes about rounding, clamp and saturate -- 2.30.2