From 2fa9c1f65f59e893064937c35a46c804b924cb55 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Wed, 17 Apr 2019 13:09:59 +0200 Subject: [PATCH] [ARC][COMMITTED] Fix diagnostic messages. Apply upper/dot rule on diagnostic messages. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.c (arc_init): Format diagnostic string. (arc_override_options): Likewise. (check_if_valid_regno_const): Likewise. (arc_reorg): Likewise. From-SVN: r270408 --- gcc/ChangeLog | 7 +++++++ gcc/config/arc/arc.c | 22 ++++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9480e693c08..3820fae8ee7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-04-17 Claudiu Zissulescu + + * config/arc/arc.c (arc_init): Format diagnostic string. + (arc_override_options): Likewise. + (check_if_valid_regno_const): Likewise. + (arc_reorg): Likewise. + 2019-04-17 Segher Boessenkool PR target/17108 diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 65eef30747a..1a04f9ef793 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -950,13 +950,13 @@ arc_init (void) /* FPX-4. No FPX extensions mixed with FPU extensions. */ if ((TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP) && TARGET_HARD_FLOAT) - error ("No FPX/FPU mixing allowed"); + error ("no FPX/FPU mixing allowed"); /* Warn for unimplemented PIC in pre-ARC700 cores, and disable flag_pic. */ if (flag_pic && TARGET_ARC600_FAMILY) { warning (0, - "PIC is not supported for %s. Generating non-PIC code only..", + "PIC is not supported for %s. Generating non-PIC code only", arc_cpu_string); flag_pic = 0; } @@ -1222,26 +1222,26 @@ arc_override_options (void) do { \ if ((!(arc_selected_cpu->arch_info->flags & CODE)) \ && (VAR == VAL)) \ - error ("Option %s=%s is not available for %s CPU.", \ + error ("option %s=%s is not available for %s CPU", \ DOC0, DOC1, arc_selected_cpu->name); \ if ((arc_selected_cpu->arch_info->dflags & CODE) \ && (VAR != DEFAULT_##VAR) \ && (VAR != VAL)) \ - warning (0, "Option %s is ignored, the default value %s" \ - " is considered for %s CPU.", DOC0, DOC1, \ + warning (0, "option %s is ignored, the default value %s" \ + " is considered for %s CPU", DOC0, DOC1, \ arc_selected_cpu->name); \ } while (0); #define ARC_OPT(NAME, CODE, MASK, DOC) \ do { \ if ((!(arc_selected_cpu->arch_info->flags & CODE)) \ && (target_flags & MASK)) \ - error ("Option %s is not available for %s CPU", \ + error ("option %s is not available for %s CPU", \ DOC, arc_selected_cpu->name); \ if ((arc_selected_cpu->arch_info->dflags & CODE) \ && (target_flags_explicit & MASK) \ && (!(target_flags & MASK))) \ - warning (0, "Unset option %s is ignored, it is always" \ - " enabled for %s CPU.", DOC, \ + warning (0, "unset option %s is ignored, it is always" \ + " enabled for %s CPU", DOC, \ arc_selected_cpu->name); \ } while (0); @@ -7268,7 +7268,8 @@ check_if_valid_regno_const (rtx *operands, int opno) case CONST_INT : return true; default: - error ("register number must be a compile-time constant. Try giving higher optimization levels"); + error ("register number must be a compile-time constant. " + "Try giving higher optimization levels"); break; } return false; @@ -8261,7 +8262,8 @@ arc_reorg (void) cfun->machine->ccfsm_current_insn = NULL_RTX; if (!INSN_ADDRESSES_SET_P()) - fatal_error (input_location, "Insn addresses not set after shorten_branches"); + fatal_error (input_location, + "insn addresses not set after shorten_branches"); for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { -- 2.30.2