From 2fb35fb3294d17a735cfafee0050281af41561b0 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Nov 2018 06:41:25 +0000
Subject: [PATCH] add compressed decoder

---
 3d_gpu/microarchitecture.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index de5fc3346..558cc0c92 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -112,3 +112,4 @@ called the flip-flops orchestrating the timing "collectors".
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
 * <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>
+* <https://github.com/ataradov/riscv/blob/master/rtl/riscv_core.v#L210>
-- 
2.30.2