From 2fc2f8a6c076658c024bfa785c5bbe30597b582b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 18 Mar 2015 14:41:43 +0100 Subject: [PATCH] migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) --- migen/genlib/io.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/genlib/io.py b/migen/genlib/io.py index cd436072..ab8cc9bf 100644 --- a/migen/genlib/io.py +++ b/migen/genlib/io.py @@ -35,7 +35,7 @@ class DifferentialOutput(Special): raise NotImplementedError("Attempted to use a differential output, but platform does not support them") class CRG(Module): - def __init__(self, clk, rst=Signal()): + def __init__(self, clk, rst=0): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) -- 2.30.2