From 2fd0aed89a6e409377065d55bf21bb1511f5f74b Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 13 Jan 2017 17:04:23 -0800 Subject: [PATCH] intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32 Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/intel/compiler/brw_fs.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 7c76c98bb0e..a564dd6ed15 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -5076,8 +5076,14 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo, type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 && type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1; + /* We check size_read(i) against size_written instead of REG_SIZE + * because we want to properly handle SIMD32. In SIMD32, you can end + * up with writes to 4 registers and a source that reads 2 registers + * and we may still need to lower all the way to SIMD8 in that case. + */ if (inst->size_written > REG_SIZE && - inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE && + inst->size_read(i) != 0 && + inst->size_read(i) < inst->size_written && !is_scalar_exception && !is_packed_word_exception) { const unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE); max_width = MIN2(max_width, inst->exec_size / reg_count); -- 2.30.2