From 300c1da03a417308a2388fad5799d5b5eec4a06a Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Tue, 16 Jun 2020 16:26:35 +0200 Subject: [PATCH] Fix variable read as an attribute --- gram/phy/ecp5ddrphy.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 9a3818d..e6c62ae 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -165,7 +165,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable): bankbits = len(self.pads.ba.o) # Init ------------------------------------------------------------------------------------- - m.submodules.init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x")) + m.submodules.init = init = DomainRenamer("init")(ECP5DDRPHYInit("sync2x")) # Parameters ------------------------------------------------------------------------------- cl, cwl = get_cl_cw("DDR3", tck) @@ -278,8 +278,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable): i_SCLK=ClockSignal("sync"), i_ECLK=ClockSignal("sync2x"), i_RST=ResetSignal("sync2x"), - i_DDRDEL=self.init.delay, - i_PAUSE=self.init.pause | self._dly_sel.w_data[i], + i_DDRDEL=init.delay, + i_PAUSE=init.pause | self._dly_sel.w_data[i], # Control # Assert LOADNs to use DDRDEL control -- 2.30.2