From 3036c8991964674ca2407c543645d841ad431267 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 4 Dec 2019 10:40:02 +0100 Subject: [PATCH] x86: drop some stray/bogus DefaultSize Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.) --- gas/ChangeLog | 7 ++++ gas/config/tc-i386.c | 4 ++- gas/testsuite/gas/i386/general.l | 55 +++++++++++++++++++++++++++----- gas/testsuite/gas/i386/general.s | 37 +++++++++++++++++++++ opcodes/ChangeLog | 7 ++++ opcodes/i386-opc.tbl | 10 +++--- opcodes/i386-tbl.h | 10 +++--- 7 files changed, 111 insertions(+), 19 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 45e8b8a8e9a..7307dc8e444 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2019-12-04 Jan Beulich + + * config/tc-i386.c (process_suffix): Exclude SYSRET alongside + FLDENV et al. + * testsuite/gas/i386/general.s: Expand .code16gcc set of insns. + * testsuite/gas/i386/general.l: Adjust expectations. + 2019-11-22 Andrew Burgess * as.c (flag_dwarf_cie_version): Change initial value to -1, and diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 120367d55d3..64312d27ab0 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6311,7 +6311,9 @@ process_suffix (void) else if (i.tm.opcode_modifier.defaultsize && !i.suffix /* exclude fldenv/frstor/fsave/fstenv */ - && i.tm.opcode_modifier.no_ssuf) + && i.tm.opcode_modifier.no_ssuf + /* exclude sysret */ + && i.tm.base_opcode != 0x0f07) { if (stackop_size == LONG_MNEM_SUFFIX && i.tm.base_opcode == 0xcf) diff --git a/gas/testsuite/gas/i386/general.l b/gas/testsuite/gas/i386/general.l index ac170960207..d5f74d11a63 100644 --- a/gas/testsuite/gas/i386/general.l +++ b/gas/testsuite/gas/i386/general.l @@ -31,6 +31,7 @@ .*:143: Warning:.* .*:144: Warning:.* .*:178: Warning:.* +.*:224: Warning:.* 1 .psize 0 2 .text 3 #test jumps and calls @@ -283,11 +284,49 @@ 217 022a 0FB6C8 movzb %al,%ecx 218 219 .code16gcc - 220 # Use 16-bit layout by default for fldenv. - 221 022d 67D920 fldenv \(%eax\) - 222 0230 67D920 fldenvs \(%eax\) - 223 0233 6766D920 fldenvl \(%eax\) - 224 - 225 # Force a good alignment. - 226 0237 00000000 00000000 .p2align 4,0 - 226 00 +[ ]*[1-9][0-9]*[ ]*# Except for IRET use 32-bit implicit stack accesses by default. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66E8FAFF FFFF[ ]+call \. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF17[ ]+call \*\(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C80000 00[ ]+enter \$0,\$0 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+CF[ ]+iret +.*Warning:.*16-bit.*iret.* +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF1F[ ]+lcall \*\(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669A0000 00000000[ ]+lcall \$0,\$0 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C9[ ]+leave +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66CB[ ]+lret +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66CA0000[ ]+lret \$0 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+666A00[ ]+push \$0 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66683412 0000[ ]+push \$0x1234 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66FF37[ ]+push \(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6660[ ]+pusha +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669C[ ]+pushf +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+668F07[ ]+pop \(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6661[ ]+popa +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+669D[ ]+popf +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C3[ ]+ret +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+66C20000[ ]+ret \$0 +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]*# However use 16-bit branches not accessing the stack by default. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+77FE[ ]+ja \. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F873012[ ]+ja \.\+0x1234 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E3FE[ ]+jcxz \. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+EBFE[ ]+jmp \. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E93112[ ]+jmp \.\+0x1234 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+FF27[ ]+jmp \*\(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+FF2F[ ]+ljmp \*\(%bx\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+EA000000 00[ ]+ljmp \$0,\$0 +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+E2FE[ ]+loop \. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F05[ ]+syscall +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F34[ ]+sysenter +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F35[ ]+sysexit +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+0F07[ ]+sysret +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+C7F8FCFF[ ]+xbegin \. +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]*# Use 16-bit layout by default for fldenv. +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+67D920[ ]+fldenv \(%eax\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+67D920[ ]+fldenvs \(%eax\) +[ ]*[1-9][0-9]*[ ]+[0-9a-f]*[ ]+6766D920[ ]+fldenvl \(%eax\) +[ ]*[1-9][0-9]*[ ]* +[ ]*[1-9][0-9]*[ ]*# Force a good alignment. +[ ]*[1-9][0-9]*[ ]+[0-9a-f ]+\.p2align 4,0 +#pass diff --git a/gas/testsuite/gas/i386/general.s b/gas/testsuite/gas/i386/general.s index e4b2530e0d1..add14fd3f2d 100644 --- a/gas/testsuite/gas/i386/general.s +++ b/gas/testsuite/gas/i386/general.s @@ -217,6 +217,43 @@ movzb %al,%ecx .code16gcc +# Except for IRET use 32-bit implicit stack accesses by default. + call . + call *(%bx) + enter $0,$0 + iret + lcall *(%bx) + lcall $0,$0 + leave + lret + lret $0 + push $0 + push $0x1234 + push (%bx) + pusha + pushf + pop (%bx) + popa + popf + ret + ret $0 + +# However use 16-bit branches not accessing the stack by default. + ja . + ja .+0x1234 + jcxz . + jmp . + jmp .+0x1234 + jmp *(%bx) + ljmp *(%bx) + ljmp $0,$0 + loop . + syscall + sysenter + sysexit + sysret + xbegin . + # Use 16-bit layout by default for fldenv. fldenv (%eax) fldenvs (%eax) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index fbd74873f26..79f12e93658 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2019-12-04 Jan Beulich + + * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only + forms. + (xbegin): Drop DefaultSize. + * i386-tbl.h: Re-generate. + 2019-11-22 Mihail Ionescu * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2ebeff98455..1d2c76b9ad2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -151,13 +151,13 @@ movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex, Reg32|Reg64 } // Push instructions. -push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +push, 1, 0x50, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S } push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 } push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } +push, 1, 0x50, None, 1, Cpu64, ShortForm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S } push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S } @@ -166,11 +166,11 @@ push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } // Pop instructions. -pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } +pop, 1, 0x58, None, 1, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 } pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex } pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg } // In 64bit mode, the operand size is implicitly 64bit. -pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } +pop, 1, 0x58, None, 1, Cpu64, ShortForm|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 } pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex } pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg } @@ -2550,7 +2550,7 @@ xrelease, 0, 0xf3, None, 1, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l // RTM instructions xabort, 1, 0xc6f8, None, 2, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } -xbegin, 1, 0xc7f8, None, 2, CpuRTM, JumpDword|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 } +xbegin, 1, 0xc7f8, None, 2, CpuRTM, JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 } xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d8ab7a898e8..8120fb9743d 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -547,7 +547,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, - { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 0, + { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, @@ -607,7 +607,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, + { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, @@ -679,7 +679,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, - { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 1, 1, 0, + { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, @@ -715,7 +715,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, - { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, + { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, @@ -42835,7 +42835,7 @@ const insn_template i386_optab[] = 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, + { 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, -- 2.30.2