From 3065418361b8b3ab3083d9874d4304a6ed5e90c5 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Jun 2022 17:50:27 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index ae0459ed4..e0b3bc63c 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -173,7 +173,8 @@ conceptualise what the effect of Twin Predication is, but it actually goes much further: in *any* twin-predicated instruction (extsw, fmv) it is possible to apply one predicate to the source register (compressing the source element array) and another *completely separate* predicate -to the destination register, *in one instruction* and not just on Load/Stores. +to the destination register, not just on Load/Stores but on *arithmetic* +operations. No other Vector ISA in the world has this capability. All true Vector ISAs have Predicate Masks: it is an absolutely essential characteristic. @@ -189,6 +190,10 @@ is that there just wasn't enough space in the 24-bits of the SVP64 Prefix. Consequently, when using a given instruction, it is necessary to look up in the ISA Tables whether it is 1P or 2P. caveat emptor! +Also worth a special mention: all Load/Store operations are Twin-Predicated. +In other words: one Predicate applies to the Array of Memory Addresses, +whilst the other Predicate applies to the Array of Memory Data. + # CR weird instructions [[sv/int_cr_predication]] is by far the biggest violator of the SVP64 -- 2.30.2