From 307de722cbedc3c079c6a06062dcc8d5392f3981 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 8 Jan 2019 20:42:56 +0000
Subject: [PATCH] back.verilog: remove undriven check.

This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.

Fixes #23.
---
 nmigen/back/verilog.py | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py
index 249075d..0b86fe3 100644
--- a/nmigen/back/verilog.py
+++ b/nmigen/back/verilog.py
@@ -29,9 +29,6 @@ proc_dff
 proc_clean
 memory_collect
 write_verilog -norename
-# Make sure there are no undriven wires in generated RTLIL.
-proc
-select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d
 """.format(il_text))
     if popen.returncode:
         raise YosysError(error.strip())
-- 
2.30.2