From 309ae98246cf9ff115b7d95ae14991faf72a5a38 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 18 Jul 2014 10:28:45 +0200 Subject: [PATCH] Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port --- passes/opt/opt_reduce.cc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 1e91d1601..a0c7a027f 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -266,6 +266,21 @@ struct OptReduceWorker mem_wren_sigs.add(assign_map(cell->connections["\\D"])); } + bool keep_expanding_mem_wren_sigs = true; + while (keep_expanding_mem_wren_sigs) { + keep_expanding_mem_wren_sigs = false; + for (auto &cell_it : module->cells) { + RTLIL::Cell *cell = cell_it.second; + if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections["\\Y"]))) { + if (!mem_wren_sigs.check_all(assign_map(cell->connections["\\A"])) || + !mem_wren_sigs.check_all(assign_map(cell->connections["\\B"]))) + keep_expanding_mem_wren_sigs = true; + mem_wren_sigs.add(assign_map(cell->connections["\\A"])); + mem_wren_sigs.add(assign_map(cell->connections["\\B"])); + } + } + } + while (did_something) { did_something = false; -- 2.30.2