From 30a3d1e975cd3df7ea701fdf0fe3bd0ba0757d3e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 28 Jul 2019 16:16:19 -0700 Subject: [PATCH] fix pipeline stage count --- src/ieee754/fpdiv/pipeline.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 68d07eef..bcd99e26 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -156,16 +156,12 @@ class FPDIVMuxInOut(ReservationStations): """ def __init__(self, width, num_rows, op_wid=2): - self.id_wid = num_bits(width) + self.id_wid = num_bits(width) # FIXME: shouldn't this be num_rows? self.pspec = PipelineSpec(width, self.id_wid, op_wid) - # get the standard mantissa width, store in the pspec HOWEVER... + # get the standard mantissa width, store in the pspec fmt = FPFormat.standard(width) log2_radix = 3 # tested options so far: 1, 2 and 3. - # TODO (depends on how many RS's we want) - #n_comb_stages = width // (2 * log2_radix) # 2 compute steps per stage - n_comb_stages = 2 # FIXME: switch back - fraction_width = fmt.fraction_width # extra bits needed: guard + round @@ -176,6 +172,8 @@ class FPDIVMuxInOut(ReservationStations): # the last stage cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix) + n_comb_stages = (cfg.n_stages + 1) // 2 # 2 compute steps per stage + self.pspec.fpformat = fmt self.pspec.n_comb_stages = n_comb_stages self.pspec.core_config = cfg -- 2.30.2