From 30bb35201ebf726934ad619a38f1b9f5df5d4bde Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Mar 2021 18:32:51 +0000 Subject: [PATCH] add in SVP64 LD/ST basic test for ISACaller --- src/soc/decoder/isa/caller.py | 4 ++++ src/soc/decoder/isa/test_caller_svp64.py | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index f7a015ad..f6c83e67 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -836,6 +836,10 @@ class ISACaller: dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {} print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname) + # get SVSTATE VL + if self.is_svp64_mode: + vl = self.svstate.vl.asint(msb0=True) + # VL=0 in SVP64 mode means "do nothing: skip instruction" if self.is_svp64_mode and vl == 0: self.pc.update(self.namespace, self.is_svp64_mode) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index 118886c1..1eebf7bf 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -21,6 +21,24 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + def test_sv_load_store(self): + lst = SVP64Asm(["addi 1, 0, 0x0010", + "addi 2, 0, 0x1234", + "sv.stw 2, 0(1)", + "sv.lwz 3, 0(1)"]) + lst = list(lst) + + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl[0:7] = 1 # VL + svstate.maxvl[0:7] = 1 # MAXVL + print ("SVSTATE", bin(svstate.spr.asint())) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate) + print(sim.gpr(1)) + self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) + def test_sv_add(self): # adds: # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 -- 2.30.2