From 30d04f82a34aeda92e83e63922ade640b43d08ec Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 26 Mar 2023 18:53:49 +0100
Subject: [PATCH]

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 openpower/sv/rfc/ls009.mdwn | 177 ++++++++++++++++++++++++++++++++++++
 1 file changed, 177 insertions(+)
 create mode 100644 openpower/sv/rfc/ls009.mdwn

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+# RFC ls009 SVP64 REMAP instructions
+
+**URLs**:
+
+* <https://libre-soc.org/openpower/sv/>
+* <https://libre-soc.org/openpower/sv/rfc/ls009/>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1040>
+* <https://git.openpower.foundation/isa/PowerISA/issues/87>
+
+**Severity**: Major
+
+**Status**: New
+
+**Date**: 24 Mar 2023
+
+**Target**: v3.2B
+
+**Source**: v3.0B
+
+**Books and Section affected**:
+
+```
+    Book I, new Zero-Overhead-Loop Chapter.
+    Appendix E Power ISA sorted by opcode
+    Appendix F Power ISA sorted by version
+    Appendix G Power ISA sorted by Compliancy Subset
+    Appendix H Power ISA sorted by mnemonic
+```
+
+**Summary**
+
+```
+    svremap  - Re-Mapping of Register Element Offsets
+    svindex  - General-purpose setting of SHAPEs to be re-mapped
+    svshape  - Hardware-level setting of SHAPEs for element re-mapping
+    svshape2 - Hardware-level setting of SHAPEs for element re-mapping (v2)
+```
+
+**Submitter**: Luke Leighton (Libre-SOC)
+
+**Requester**: Libre-SOC
+
+**Impact on processor**:
+
+```
+    Addition of four new "Zero-Overhead-Loop-Control" DSP-style Vector-style
+    Management Instructions which provide advanced features such as Matrix
+    FFT DCT Hardware-Assist Schedules and general-purpose Index reordering.
+```
+
+**Impact on software**:
+
+```
+    Requires support for new instructions in assembler, debuggers,
+    and related tools.
+```
+
+**Keywords**:
+
+```
+    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
+    Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
+    Digital Signal Processing (DSP)
+```
+
+**Motivation**
+
+These REMAP Management instructions provide state-of-the-art advanced capabilities
+to dramatically decrease instruction count and power reduction whilst retaining
+unprecedented general-purpose capability and a standard Sequential Execution Model.
+
+**Notes and Observations**:
+
+1. TODO
+
+**Changes**
+
+Add the following entries to:
+
+* the Appendices of Book I
+* Instructions of Book I as a new Section
+* TODO-Form of Book I Section 1.6.1.6 and 1.6.2
+
+----------------
+
+\newpage{}
+
+# svstep: Vertical-First Stepping and status reporting
+
+SVL-Form
+
+* svstep RT,SVi,vf (Rc=0)
+* svstep. RT,SVi,vf (Rc=1)
+
+| 0-5|6-10|11.15|16..22| 23-25    | 26-30 |31|   Form   |
+|----|----|-----|------|----------|-------|--|--------- |
+|PO  | RT | /   | SVi  |  / / vf  | XO    |Rc| SVL-Form |
+
+Pseudo-code:
+
+```
+    if SVi[3:4] = 0b11 then
+        # store pack and unpack in SVSTATE
+        SVSTATE[53] <- SVi[5]
+        SVSTATE[54] <- SVi[6]
+        RT <- [0]*62 || SVSTATE[53:54]
+    else
+        # Vertical-First explicit stepping.
+        step <- SVSTATE_NEXT(SVi, vf)
+        RT <- [0]*57 || step
+```
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
+**Description**
+
+
+-------------
+
+\newpage{}
+
+
+-------------
+
+\newpage{}
+
+# SVL-Form
+
+Add the following to Book I, 1.6.1, SVL-Form
+
+```
+    |0     |6    |11    |16   |23 |24 |25 |26    |31 |
+    | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
+    | PO   |  RT | /    | SVi |/  |/  |vf |   XO |Rc |
+```
+
+* Add `SVL` to `RA (11:15)` Field in Book I, 1.6.2
+* Add `SVL` to `RT (6:10)` Field in Book I, 1.6.2
+* Add `SVL` to `Rc (31)` Field in Book I, 1.6.2
+* Add `SVL` to `XO (26:31)` Field in Book I, 1.6.2
+
+Add the following to Book I, 1.6.2
+
+```
+    ms (23)
+        Field used in Simple-V to specify whether MVL (maxvl in the SVSTATE SPR)
+        is to be set
+        Formats: SVL
+    vf (25)
+        Field used in Simple-V to specify whether "Vertical" Mode is set
+        (vfirst in the SVSTATE SPR)
+        Formats: SVL
+    vs (24)
+        Field used in Simple-V to specify whether VL (vl in the SVSTATE SPR) is to be set
+        Formats: SVL
+    SVi (16:22)
+         Simple-V immediate field used by setvl for setting VL or MVL
+         (vl, maxvl in the SVSTATE SPR)
+         and used as a "Mode of Operation" selector in svstep
+         Formats: SVL
+```
+
+# Appendices
+
+    Appendix E Power ISA sorted by opcode
+    Appendix F Power ISA sorted by version
+    Appendix G Power ISA sorted by Compliancy Subset
+    Appendix H Power ISA sorted by mnemonic
+
+| Form | Book | Page | Version | mnemonic | Description |
+|------|------|------|---------|----------|-------------|
+| SVL  | I    | #    | 3.0B    | svstep   | Vertical-First Stepping and status reporting |
+| SVL  | I    | #    | 3.0B    | setvl    | Cray-like establishment of Looping (Vector) context |
+
+[[!tag opf_rfc]]
-- 
2.30.2