From 30d718c2fbaeeffb24468ce773e44a6bf6f6aa2a Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Fri, 29 Aug 2014 17:22:57 -0700 Subject: [PATCH] i965/fs: Use the instruction execution size directly for texture generation Signed-off-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 36a51fdc55f..7c6f487c67c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -388,7 +388,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src { int msg_type = -1; int rlen = 4; - uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + uint32_t simd_mode; uint32_t return_format; switch (dst.type) { @@ -403,9 +403,16 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src break; } - if (dispatch_width == 16 && - !inst->force_uncompressed && !inst->force_sechalf) + switch (inst->exec_size) { + case 8: + simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + break; + case 16: simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + break; + default: + unreachable("Invalid width for texture instruction"); + } if (brw->gen >= 5) { switch (inst->opcode) { -- 2.30.2