From 30da7b114581e5259ada027197f868f5b8b61609 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 21 Mar 2021 13:18:30 +0000 Subject: [PATCH] adjust syntax of SVP64 predicate test cas --- src/soc/fu/alu/test/svp64_cases.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index 4ae5e8ae..3b42ef4a 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -228,7 +228,7 @@ class SVP64ALUTestCase(TestAccumulatorBase): # expected results: # r5 = 0x0 dest r3 is 0b10: skip # r6 = 0xffff_ffff_ffff_ff91 2nd bit of r3 is 1 - isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v']) + isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v']) lst = list(isa) print("listing", lst) -- 2.30.2