From 30dc0548674e879ee7b52474a662bc25c70e8802 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 18 Jun 2020 16:11:10 -0700
Subject: [PATCH] div pipe completed except for tests

---
 src/soc/fu/div/core_stages.py |  3 ++
 src/soc/fu/div/pipeline.py    | 56 ++++++++++++++++++++++++++---------
 2 files changed, 45 insertions(+), 14 deletions(-)

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index cc4e6f7e..3bbde7db 100644
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -15,6 +15,9 @@ from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage)
 
+__all__ = ["DivCoreBaseStage", "DivCoreSetupStage",
+           "DivCoreCalculateStage", "DivCoreFinalStage"]
+
 
 class DivCoreBaseStage(PipeModBase):
     def __init__(self, pspec, modname, core_class, *args, **kwargs):
diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index 3bde19bd..fb510ff0 100644
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -1,33 +1,61 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
 from soc.fu.alu.input_stage import ALUInputStage
-from soc.fu.logical.main_stage import LogicalMainStage
 from soc.fu.alu.output_stage import ALUOutputStage
+from soc.fu.div.setup_stage import DivSetupStage
+from soc.fu.div.core_stages import DivCoreSetupStage, DivCoreCalculateStage, DivCoreFinalStage
+from soc.fu.div.output_stage import DivOutputStage
 
 
 class DivStagesStart(PipeModBaseChain):
     def get_chain(self):
-        inp = ALUInputStage(self.pspec)
-        main = DivMainStage1(self.pspec)
-        return [inp, main, out]
+        alu_input = ALUInputStage(self.pspec)
+        div_setup = DivSetupStage(self.pspec)
+        core_setup = DivCoreSetupStage(self.pspec)
+        return [alu_input, div_setup, core_setup]
+
+
+class DivStagesMiddle(PipeModBaseChain):
+    def __init__(self, pspec, stage_start_index, stage_end_index):
+        self.stage_start_index = stage_start_index
+        self.stage_end_index = stage_end_index
+        super().__init__(pspec)
+
+    def get_chain(self):
+        stages = []
+        for index in range(self.stage_start_index, self.stage_end_index):
+            stages.append(DivCoreCalculateStage(self.pspec, index))
+        return stages
+
 
 class DivStagesEnd(PipeModBaseChain):
     def get_chain(self):
-        main = DivMainStage2(self.pspec)
-        out = ALUOutputStage(self.pspec)
-        return [inp, main, out]
+        core_final = DivCoreFinalStage(self.pspec)
+        div_out = DivOutputStage(self.pspec)
+        alu_out = ALUOutputStage(self.pspec)
+        return [core_final, div_out, alu_out]
 
 
-class LogicalBasePipe(ControlBase):
-    def __init__(self, pspec):
+class DivPipe(ControlBase):
+    def __init__(self, pspec, compute_steps_per_stage=2):
         ControlBase.__init__(self)
-        self.pipe1 = DivStagesStart(pspec)
-        self.pipe5 = DivStagesEnd(pspec)
-        self._eqs = self.connect([self.pipe1, self.pipe5])
+        self.pipe_start = DivStagesStart(pspec)
+        compute_steps = pspec.core_config.n_stages
+        self.pipe_middles = []
+        for start in range(0, compute_steps, compute_steps_per_stage):
+            end = min(start + compute_steps_per_stage, compute_steps)
+            self.pipe_middles.append(DivStagesMiddle(pspec, start, end))
+        self.pipe_end = DivStagesEnd(pspec)
+        self._eqs = self.connect([self.pipe_start,
+                                  *self.pipe_middles,
+                                  self.pipe_end])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe1 = self.pipe1
-        m.submodules.pipe5 = self.pipe5
+        m.submodules.pipe_start = self.pipe_start
+        for i in self.pipe_middles:
+            name = f"pipe_{i.stage_start_index}_to_{i.stage_end_index}"
+            setattr(m.submodules, name, i)
+        m.submodules.pipe_end = self.pipe_end
         m.d.comb += self._eqs
         return m
-- 
2.30.2