From 30df7338861724f543fb10dfcee8c62d855250a5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 11 Nov 2021 10:30:11 +0000 Subject: [PATCH] sort out numbering on CRs in SimState --- src/openpower/test/state.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index 59c976b7..37859819 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -146,7 +146,7 @@ class SimState(State): yield self.crregs = [] for i in range(8): - cri = self.sim.crl[7 - i].get_range().value + cri = self.sim.crl[i].get_range().value self.crregs.append(cri) log("class sim cr regs", list(map(hex, self.crregs))) @@ -240,7 +240,7 @@ class ExpectedState(State): sout.write( msg % (lindent, i, reg)) # CR fields for i in range(8): - cri = state.crregs[i] # Power ISA numbering already sorted + cri = state.crregs[i] if(cri != 0): msg = "%se.crregs[%d] = 0x%x\n" sout.write( msg % (lindent, i, cri)) -- 2.30.2