From 30e3816aafe77ccda915660114ff77f584f8e1a2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Sep 2018 06:28:04 +0100 Subject: [PATCH] add reference to vector length in sv --- riscv/insn_template.cc | 6 ++++-- riscv/sv_decode.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc index 354c0d9..8856aab 100644 --- a/riscv/insn_template.cc +++ b/riscv/insn_template.cc @@ -12,7 +12,8 @@ reg_t rv32_NAME(processor_t* p, insn_t s_insn, reg_t pc) reg_t npc = sext_xlen(pc + insn_length(OPCODE)); insn_bits_t bits = s_insn.bits(); #ifdef SPIKE_SIMPLEV - sv_insn_t insn(bits); + int vlen = 1; + sv_insn_t insn(bits, vlen); #include "insns/NAME.h" trace_opcode(p, OPCODE, s_insn); #else @@ -29,7 +30,8 @@ reg_t rv64_NAME(processor_t* p, insn_t s_insn, reg_t pc) reg_t npc = sext_xlen(pc + insn_length(OPCODE)); insn_bits_t bits = s_insn.bits(); #ifdef SPIKE_SIMPLEV - sv_insn_t insn(bits); + int vlen = 1; + sv_insn_t insn(bits, vlen); #include "insns/NAME.h" trace_opcode(p, OPCODE, s_insn); #else diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index e8eee26..73a2941 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -9,12 +9,13 @@ class sv_insn_t: public insn_t { public: - sv_insn_t(insn_bits_t bits) : insn_t(bits) {} + sv_insn_t(insn_bits_t bits, int& v) : insn_t(bits), vlen(v) {} uint64_t rd () { return remap(insn_t::rd()); } uint64_t rs1() { return remap(insn_t::rs1()); } uint64_t rs2() { return remap(insn_t::rs2()); } uint64_t rs3() { return remap(insn_t::rs3()); } private: + int &vlen; // remaps the register through the lookup table. // will need to take the current loop index/offset somehow uint64_t remap(uint64_t reg) { return reg; } // TODO -- 2.30.2