From 30e777a5d3829975266ecccac965d2297a5f4985 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 4 Aug 2007 20:24:18 -0700
Subject: [PATCH] X86: Implement microops and instructions that manipulate the
 flags register.

--HG--
extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203
---
 src/arch/x86/isa/decoder/one_byte_opcodes.isa | 12 +++---
 src/arch/x86/isa/insts/flags/set_and_clear.py | 43 ++++++++++++++-----
 src/arch/x86/isa/insts/semaphores.py          |  6 ---
 src/arch/x86/isa/microops/regop.isa           |  4 ++
 src/arch/x86/isa/specialize.isa               |  4 ++
 src/arch/x86/miscregs.hh                      |  1 +
 6 files changed, 47 insertions(+), 23 deletions(-)

diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 7c627b0c2..cce07d6fe 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -529,13 +529,13 @@
             }
         }
         0x1F: decode OPCODE_OP_BOTTOM3 {
-            0x0: clc();
-            0x1: stc();
-            0x2: cli();
-            0x3: sti();
-            0x4: cld();
-            0x5: std();
             format Inst {
+                0x0: CLC();
+                0x1: STC();
+                0x2: WarnUnimpl::cli();
+                0x3: WarnUnimpl::sti();
+                0x4: CLD();
+                0x5: STD();
                 //0x6: group4();
                 0x6: decode MODRM_REG {
                     0x0: INC(Eb);
diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py
index d70b95382..4c655e0b2 100644
--- a/src/arch/x86/isa/insts/flags/set_and_clear.py
+++ b/src/arch/x86/isa/insts/flags/set_and_clear.py
@@ -53,18 +53,39 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CLD {
+    ruflags t1
+    limm t2, "~((uint64_t)DFBit)"
+    and t1, t1, t2
+    wruflags t1, t0
+};
+
+def macroop STD {
+    ruflags t1
+    limm t2, "DFBit"
+    or t1, t1, t2
+    wruflags t1, t0
+};
+
+def macroop CLC {
+    ruflags t1
+    andi t2, t1, "CFBit"
+    wruflags t1, t2
+};
+
+def macroop STC {
+    ruflags t1
+    ori t1, t1, "CFBit"
+    wruflags t1, t0
+};
+
+def macroop CMC {
+    ruflags t1
+    wruflagsi t1, "CFBit"
+};
+'''
 #let {{
-#    class CLC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class CMC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class STC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class CLD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class STD(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #    class CLI(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class STI(Inst):
diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py
index 882213a3f..800f1b325 100644
--- a/src/arch/x86/isa/insts/semaphores.py
+++ b/src/arch/x86/isa/insts/semaphores.py
@@ -80,12 +80,6 @@ def macroop CMPXCHG_P_R {
 };
 '''
 #let {{
-#    class CMPXCHG(Inst):
-# 	"GenFault ${new UnimpInstFault}"
-#    class CMPXCHG8B(Inst):
-# 	"GenFault ${new UnimpInstFault}"
-#    class CMPXCHG16B(Inst):
-# 	"GenFault ${new UnimpInstFault}"
 #    class XADD(Inst):
 # 	"GenFault ${new UnimpInstFault}"
 #    class XCHG(Inst):
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 3c562efc0..ac88be657 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -615,8 +615,12 @@ let {{
             ''')
 
     defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
+    defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
 
     defineMicroRegOpRd('Rdip', 'DestReg = RIP')
+    defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
+    defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
+            flagCode = genCCFlagBitsLogic)
 
     defineMicroRegOpImm('Sext', '''
             IntReg val = psrc1;
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 690061de7..59e9577d9 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -176,6 +176,10 @@ let {{
                 # Non register modrm settings should cause an error
                 env.addReg(ModRMRMIndex)
                 Name += "_R"
+            elif opType.tag in ("X", "Y"):
+                # This type of memory addressing is for string instructions.
+                # They'll use the right index and segment internally.
+                Name += "_M"
             else:
                 raise Exception, "Unrecognized tag %s." % opType.tag
 
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index b2294292e..8792bf6dd 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -70,6 +70,7 @@ namespace X86ISA
         EZFBit = 1 << 5,
         ZFBit = 1 << 6,
         SFBit = 1 << 7,
+        DFBit = 1 << 10,
         OFBit = 1 << 11
     };
 
-- 
2.30.2