From 30f1204721ed592256ddde04f22dd40888b9e27c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 16 Feb 2019 22:22:17 -0800 Subject: [PATCH] Cleanup --- backends/aiger/xaiger.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ae296d395..d4686736d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -521,7 +521,7 @@ struct XAigerWriter for (int i = 0; i < GetSize(wire); i++) { - if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr) + if (aig_map.count(sig[i]) == 0 /*|| sig[i].wire == nullptr*/) continue; int a = aig_map.at(sig[i]); @@ -529,13 +529,14 @@ struct XAigerWriter if (verbose_map) wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire)); - if (wire->port_input || ci_bits.count(RTLIL::SigBit{wire, i})) { + RTLIL::SigBit b(wire, i); + if (wire->port_input || ci_bits.count(b)) { log_assert((a & 1) == 0); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); } - if (output_bits.count(RTLIL::SigBit{wire, i}) || co_bits.count(RTLIL::SigBit{wire, i})) { - int o = ordered_outputs.at(sig[i]); + if (output_bits.count(b) || co_bits.count(b)) { + int o = ordered_outputs.at(b); output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); } -- 2.30.2