From 30f8d6c85037484e3e7f28d031c93976f0f29ce5 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 30 Jul 2020 12:49:23 +0000
Subject: [PATCH] stack of signals that should not have been connected
 externally gone now

---
 experiments9/non_generated/test_issuer.il | 9838 ++++++++-------------
 1 file changed, 3712 insertions(+), 6126 deletions(-)

diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il
index 7cfde61..86f1d3a 100644
--- a/experiments9/non_generated/test_issuer.il
+++ b/experiments9/non_generated/test_issuer.il
@@ -30727,92 +30727,54 @@ module \dec
   attribute \enum_value_11 "cx"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
   wire width 2 output 23 \upd
-  attribute \enum_base_type "Form"
-  attribute \enum_value_00000 "NONE"
-  attribute \enum_value_00001 "I"
-  attribute \enum_value_00010 "B"
-  attribute \enum_value_00011 "SC"
-  attribute \enum_value_00100 "D"
-  attribute \enum_value_00101 "DS"
-  attribute \enum_value_00110 "DQ"
-  attribute \enum_value_00111 "DX"
-  attribute \enum_value_01000 "X"
-  attribute \enum_value_01001 "XL"
-  attribute \enum_value_01010 "XFX"
-  attribute \enum_value_01011 "XFL"
-  attribute \enum_value_01100 "XX1"
-  attribute \enum_value_01101 "XX2"
-  attribute \enum_value_01110 "XX3"
-  attribute \enum_value_01111 "XX4"
-  attribute \enum_value_10000 "XS"
-  attribute \enum_value_10001 "XO"
-  attribute \enum_value_10010 "A"
-  attribute \enum_value_10011 "M"
-  attribute \enum_value_10100 "MD"
-  attribute \enum_value_10101 "MDS"
-  attribute \enum_value_10110 "VA"
-  attribute \enum_value_10111 "VC"
-  attribute \enum_value_11000 "VX"
-  attribute \enum_value_11001 "EVX"
-  attribute \enum_value_11010 "EVS"
-  attribute \enum_value_11011 "Z22"
-  attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
-  wire width 5 output 24 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 25 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 26 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
-  wire width 8 output 27 \asmcode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 28 \RS
+  wire width 5 output 24 \RS
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 29 \RT
+  wire width 5 output 25 \RT
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 30 \RA
+  wire width 5 output 26 \RA
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 31 \RB
+  wire width 5 output 27 \RB
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 16 output 32 \SI
+  wire width 16 output 28 \SI
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 16 output 33 \UI
+  wire width 16 output 29 \UI
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 34 \SH32
+  wire width 5 output 30 \SH32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 6 output 35 \sh
+  wire width 6 output 31 \sh
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 24 output 36 \LI
+  wire width 24 output 32 \LI
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 1 output 37 \Rc
+  wire width 1 output 33 \Rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 1 output 38 \OE
+  wire width 1 output 34 \OE
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 14 output 39 \BD
+  wire width 14 output 35 \BD
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 40 \BB
+  wire width 5 output 36 \BB
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 41 \BA
+  wire width 5 output 37 \BA
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 42 \BT
+  wire width 5 output 38 \BT
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 43 \BO
+  wire width 5 output 39 \BO
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 44 \BI
+  wire width 5 output 40 \BI
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 14 output 45 \DS
+  wire width 14 output 41 \DS
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 5 output 46 \BC
+  wire width 5 output 42 \BC
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 10 output 47 \SPR
+  wire width 10 output 43 \SPR
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
-  wire width 3 output 48 \X_BF
+  wire width 3 output 44 \X_BF
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
-  wire width 3 output 49 \X_BFA
+  wire width 3 output 45 \X_BFA
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
-  wire width 5 output 50 \XL_BT
+  wire width 5 output 46 \XL_BT
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
-  wire width 10 output 51 \XL_XO
+  wire width 10 output 47 \XL_XO
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
   wire width 32 \dec19_opcode_in
   attribute \enum_base_type "Function"
@@ -32264,6 +32226,38 @@ module \dec
     end
     sync init
   end
+  attribute \enum_base_type "Form"
+  attribute \enum_value_00000 "NONE"
+  attribute \enum_value_00001 "I"
+  attribute \enum_value_00010 "B"
+  attribute \enum_value_00011 "SC"
+  attribute \enum_value_00100 "D"
+  attribute \enum_value_00101 "DS"
+  attribute \enum_value_00110 "DQ"
+  attribute \enum_value_00111 "DX"
+  attribute \enum_value_01000 "X"
+  attribute \enum_value_01001 "XL"
+  attribute \enum_value_01010 "XFX"
+  attribute \enum_value_01011 "XFL"
+  attribute \enum_value_01100 "XX1"
+  attribute \enum_value_01101 "XX2"
+  attribute \enum_value_01110 "XX3"
+  attribute \enum_value_01111 "XX4"
+  attribute \enum_value_10000 "XS"
+  attribute \enum_value_10001 "XO"
+  attribute \enum_value_10010 "A"
+  attribute \enum_value_10011 "M"
+  attribute \enum_value_10100 "MD"
+  attribute \enum_value_10101 "MDS"
+  attribute \enum_value_10110 "VA"
+  attribute \enum_value_10111 "VC"
+  attribute \enum_value_11000 "VX"
+  attribute \enum_value_11001 "EVX"
+  attribute \enum_value_11010 "EVS"
+  attribute \enum_value_11011 "Z22"
+  attribute \enum_value_11100 "Z23"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
+  wire width 5 \form
   process $group_7
     assign \form 5'00000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
@@ -34678,6 +34672,8 @@ module \dec
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \rsrv
   process $group_24
     assign \rsrv 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
@@ -35246,6 +35242,8 @@ module \dec
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \sgl_pipe
   process $group_28
     assign \sgl_pipe 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
@@ -35388,6 +35386,8 @@ module \dec
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
+  wire width 8 \asmcode
   process $group_29
     assign \asmcode 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292"
@@ -42564,7 +42564,7 @@ module \pdecode2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 10 output 58 \spro
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
-  wire width 32 output 59 \opcode_in
+  wire width 32 \dec_opcode_in
   attribute \enum_base_type "In1Sel"
   attribute \enum_value_000 "NONE"
   attribute \enum_value_001 "RA"
@@ -42572,7 +42572,7 @@ module \pdecode2
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
-  wire width 3 output 60 \in1_sel
+  wire width 3 \dec_in1_sel
   attribute \enum_base_type "In2Sel"
   attribute \enum_value_0000 "NONE"
   attribute \enum_value_0001 "RB"
@@ -42589,26 +42589,26 @@ module \pdecode2
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
-  wire width 4 output 61 \in2_sel
+  wire width 4 \dec_in2_sel
   attribute \enum_base_type "In3Sel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
-  wire width 2 output 62 \in3_sel
+  wire width 2 \dec_in3_sel
   attribute \enum_base_type "OutSel"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
-  wire width 2 output 63 \out_sel
+  wire width 2 \dec_out_sel
   attribute \enum_base_type "RC"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
-  wire width 2 output 64 \rc_sel
+  wire width 2 \dec_rc_sel
   attribute \enum_base_type "CRInSel"
   attribute \enum_value_000 "NONE"
   attribute \enum_value_001 "CR0"
@@ -42618,7 +42618,7 @@ module \pdecode2
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
-  wire width 3 output 65 \cr_in
+  wire width 3 \dec_cr_in
   attribute \enum_base_type "CROutSel"
   attribute \enum_value_000 "NONE"
   attribute \enum_value_001 "CR0"
@@ -42626,7 +42626,7 @@ module \pdecode2
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
-  wire width 3 output 66 \cr_out$5
+  wire width 3 \dec_cr_out
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -42701,7 +42701,7 @@ module \pdecode2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
-  wire width 7 output 67 \internal_op
+  wire width 7 \dec_internal_op
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -42715,19 +42715,7 @@ module \pdecode2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
-  wire width 11 output 68 \function_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 69 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 70 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 71 \spro_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 72 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 73 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 74 \cr_out_ok
+  wire width 11 \dec_function_unit
   attribute \enum_base_type "LdstLen"
   attribute \enum_value_0000 "NONE"
   attribute \enum_value_0001 "is1B"
@@ -42735,73 +42723,31 @@ module \pdecode2
   attribute \enum_value_0100 "is4B"
   attribute \enum_value_1000 "is8B"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
-  wire width 4 output 75 \ldst_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 76 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 77 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 78 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 79 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 80 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 81 \lk$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 82 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 83 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
-  wire width 1 output 84 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
-  wire width 8 output 85 \asmcode
-  attribute \enum_base_type "Form"
-  attribute \enum_value_00000 "NONE"
-  attribute \enum_value_00001 "I"
-  attribute \enum_value_00010 "B"
-  attribute \enum_value_00011 "SC"
-  attribute \enum_value_00100 "D"
-  attribute \enum_value_00101 "DS"
-  attribute \enum_value_00110 "DQ"
-  attribute \enum_value_00111 "DX"
-  attribute \enum_value_01000 "X"
-  attribute \enum_value_01001 "XL"
-  attribute \enum_value_01010 "XFX"
-  attribute \enum_value_01011 "XFL"
-  attribute \enum_value_01100 "XX1"
-  attribute \enum_value_01101 "XX2"
-  attribute \enum_value_01110 "XX3"
-  attribute \enum_value_01111 "XX4"
-  attribute \enum_value_10000 "XS"
-  attribute \enum_value_10001 "XO"
-  attribute \enum_value_10010 "A"
-  attribute \enum_value_10011 "M"
-  attribute \enum_value_10100 "MD"
-  attribute \enum_value_10101 "MDS"
-  attribute \enum_value_10110 "VA"
-  attribute \enum_value_10111 "VC"
-  attribute \enum_value_11000 "VX"
-  attribute \enum_value_11001 "EVX"
-  attribute \enum_value_11010 "EVS"
-  attribute \enum_value_11011 "Z22"
-  attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
-  wire width 5 output 86 \form
+  wire width 4 \dec_ldst_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 87 \rsrv
+  wire width 1 \dec_inv_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 88 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
-  wire width 8 output 89 \asmcode$7
+  wire width 1 \dec_inv_out
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134"
   wire width 2 \dec_cry_in
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_cry_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_is_32b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_sgn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 1 \dec_LK
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_br
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
+  wire width 1 \dec_sgn_ext
   attribute \enum_base_type "LDSTMode"
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "update"
@@ -42860,32 +42806,28 @@ module \pdecode2
   cell \dec \dec
     connect \bigendian \bigendian
     connect \raw_opcode_in \raw_opcode_in
-    connect \opcode_in \opcode_in
-    connect \in1_sel \in1_sel
-    connect \in2_sel \in2_sel
-    connect \in3_sel \in3_sel
-    connect \out_sel \out_sel
-    connect \rc_sel \rc_sel
-    connect \cr_in \cr_in
-    connect \cr_out \cr_out$5
-    connect \internal_op \internal_op
-    connect \function_unit \function_unit
-    connect \ldst_len \ldst_len
-    connect \inv_a \inv_a
-    connect \inv_out \inv_out
+    connect \opcode_in \dec_opcode_in
+    connect \in1_sel \dec_in1_sel
+    connect \in2_sel \dec_in2_sel
+    connect \in3_sel \dec_in3_sel
+    connect \out_sel \dec_out_sel
+    connect \rc_sel \dec_rc_sel
+    connect \cr_in \dec_cr_in
+    connect \cr_out \dec_cr_out
+    connect \internal_op \dec_internal_op
+    connect \function_unit \dec_function_unit
+    connect \ldst_len \dec_ldst_len
+    connect \inv_a \dec_inv_a
+    connect \inv_out \dec_inv_out
     connect \cry_in \dec_cry_in
-    connect \cry_out \cry_out
-    connect \is_32b \is_32b
-    connect \sgn \sgn
-    connect \lk \lk$6
+    connect \cry_out \dec_cry_out
+    connect \is_32b \dec_is_32b
+    connect \sgn \dec_sgn
+    connect \lk \dec_lk
     connect \LK \dec_LK
-    connect \br \br
-    connect \sgn_ext \sgn_ext
+    connect \br \dec_br
+    connect \sgn_ext \dec_sgn_ext
     connect \upd \dec_upd
-    connect \form \form
-    connect \rsrv \rsrv
-    connect \sgl_pipe \sgl_pipe
-    connect \asmcode \asmcode$7
     connect \RS \dec_RS
     connect \RT \dec_RT
     connect \RA \dec_RA
@@ -43046,7 +42988,7 @@ module \pdecode2
   wire width 1 \dec_a_fast_a_ok
   cell \dec_a \dec_a
     connect \sel_in \dec_a_sel_in
-    connect \internal_op \internal_op
+    connect \internal_op \dec_internal_op
     connect \reg_a \dec_a_reg_a
     connect \reg_a_ok \dec_a_reg_a_ok
     connect \immz_out \dec_a_immz_out
@@ -43091,7 +43033,7 @@ module \pdecode2
   wire width 1 \dec_b_fast_b_ok
   cell \dec_b \dec_b
     connect \sel_in \dec_b_sel_in
-    connect \internal_op \internal_op
+    connect \internal_op \dec_internal_op
     connect \reg_b \dec_b_reg_b
     connect \reg_b_ok \dec_b_reg_b_ok
     connect \imm_b \dec_b_imm_b
@@ -43258,7 +43200,7 @@ module \pdecode2
   wire width 1 \dec_o_fast_o_ok
   cell \dec_o \dec_o
     connect \sel_in \dec_o_sel_in
-    connect \internal_op \internal_op
+    connect \internal_op \dec_internal_op
     connect \reg_o \dec_o_reg_o
     connect \reg_o_ok \dec_o_reg_o_ok
     connect \spr_o \dec_o_spr_o
@@ -43282,7 +43224,7 @@ module \pdecode2
   wire width 1 \dec_o2_fast_o_ok
   cell \dec_o2 \dec_o2
     connect \lk \dec_o2_lk
-    connect \internal_op \internal_op
+    connect \internal_op \dec_internal_op
     connect \reg_o \dec_o2_reg_o
     connect \reg_o_ok \dec_o2_reg_o_ok
     connect \fast_o \dec_o2_fast_o
@@ -43318,7 +43260,7 @@ module \pdecode2
   wire width 1 \dec_oe_oe_ok
   cell \dec_oe \dec_oe
     connect \sel_in \dec_oe_sel_in
-    connect \internal_op \internal_op
+    connect \internal_op \dec_internal_op
     connect \oe \dec_oe_oe
     connect \oe_ok \dec_oe_oe_ok
     connect \OE \dec_OE
@@ -43347,7 +43289,7 @@ module \pdecode2
   wire width 1 \dec_cr_in_cr_bitfield_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
   wire width 1 \dec_cr_in_whole_reg
-  cell \dec_cr_in \dec_cr_in
+  cell \dec_cr_in \dec_cr_in$5
     connect \sel_in \dec_cr_in_sel_in
     connect \cr_bitfield \dec_cr_in_cr_bitfield
     connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok
@@ -43379,7 +43321,7 @@ module \pdecode2
   wire width 1 \dec_cr_out_cr_bitfield_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
   wire width 1 \dec_cr_out_whole_reg
-  cell \dec_cr_out \dec_cr_out
+  cell \dec_cr_out \dec_cr_out$6
     connect \sel_in \dec_cr_out_sel_in
     connect \rc_in \dec_cr_out_rc_in
     connect \cr_bitfield \dec_cr_out_cr_bitfield
@@ -43388,51 +43330,67 @@ module \pdecode2
     connect \X_BF \dec_X_BF
     connect \XL_BT \dec_XL_BT
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \rego_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \ea_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \spro_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fasto1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fasto2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_out_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
+  wire width 1 \xer_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
+  wire width 8 \asmcode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-  wire width 1 $8
+  wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-  cell $eq $9
+  cell $eq $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \internal_op
+    connect \A \dec_internal_op
     connect \B 7'0101110
-    connect \Y $8
+    connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-  wire width 1 $10
+  wire width 1 $9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-  cell $eq $11
+  cell $eq $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \internal_op
+    connect \A \dec_internal_op
     connect \B 7'0110001
-    connect \Y $10
+    connect \Y $9
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-  wire width 1 $12
+  wire width 1 $11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-  cell $eq $13
+  cell $eq $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \internal_op
+    connect \A \dec_internal_op
     connect \B 7'0111111
-    connect \Y $12
+    connect \Y $11
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:37"
   wire width 1 \is_priv_insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-  wire width 1 $14
+  wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-  cell $and $15
+  cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -43440,25 +43398,25 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \is_priv_insn
     connect \B \msr [14]
-    connect \Y $14
+    connect \Y $13
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
-  wire width 1 $16
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
-  cell $eq $17
+  cell $eq $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \internal_op
+    connect \A \dec_internal_op
     connect \B 7'0000000
-    connect \Y $16
+    connect \Y $15
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
-  wire width 1 $18
+  wire width 1 $17
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
-  cell $eq $19
+  cell $eq $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43466,12 +43424,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'0111111
-    connect \Y $18
+    connect \Y $17
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  wire width 1 $20
+  wire width 1 $19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  cell $eq $21
+  cell $eq $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43479,25 +43437,25 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'1001001
-    connect \Y $20
+    connect \Y $19
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  wire width 1 $22
+  wire width 1 $21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  cell $or $23
+  cell $or $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $18
-    connect \B $20
-    connect \Y $22
+    connect \A $17
+    connect \B $19
+    connect \Y $21
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-  wire width 1 $24
+  wire width 1 $23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-  cell $eq $25
+  cell $eq $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43505,7 +43463,7 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'1000110
-    connect \Y $24
+    connect \Y $23
   end
   process $group_82
     assign \insn 32'00000000000000000000000000000000
@@ -43571,11 +43529,11 @@ module \pdecode2
     assign \trapaddr 13'0000000000000
     assign \asmcode 8'00000000
     assign \traptype 5'00000
-    assign \insn \opcode_in
+    assign \insn \dec_opcode_in
     assign \msr$3 \msr
     assign \cia$2 \cia
-    assign \insn_type \internal_op
-    assign \fn_unit \function_unit
+    assign \insn_type \dec_internal_op
+    assign \fn_unit \dec_function_unit
     assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a }
     assign { \reg2_ok \reg2 } { \dec_b_reg_b_ok \dec_b_reg_b }
     assign { \reg3_ok \reg3 } { \dec_c_reg_c_ok \dec_c_reg_c }
@@ -43598,26 +43556,26 @@ module \pdecode2
     assign \read_cr_whole \dec_cr_in_whole_reg
     assign \write_cr_whole \dec_cr_out_whole_reg
     assign \write_cr0 \dec_cr_out_cr_bitfield_ok
-    assign \data_len \ldst_len
-    assign \invert_a \inv_a
-    assign \invert_out \inv_out
+    assign \data_len \dec_ldst_len
+    assign \invert_a \dec_inv_a
+    assign \invert_out \dec_inv_out
     assign \input_carry \dec_cry_in
-    assign \output_carry \cry_out
-    assign \is_32bit \is_32b
-    assign \is_signed \sgn
+    assign \output_carry \dec_cry_out
+    assign \is_32bit \dec_is_32b
+    assign \is_signed \dec_sgn
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
-    switch { \lk$6 }
+    switch { \dec_lk }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
       case 1'1
         assign \lk \dec_LK
     end
     switch { }
       case
-        assign \byte_reverse \br
+        assign \byte_reverse \dec_br
     end
     switch { }
       case
-        assign \sign_extend \sgn_ext
+        assign \sign_extend \dec_sgn_ext
     end
     switch { }
       case
@@ -43625,36 +43583,36 @@ module \pdecode2
     end
     switch { }
       case
-        assign \input_cr \cr_in [0]
+        assign \input_cr \dec_cr_in [0]
     end
     switch { }
       case
-        assign \output_cr \cr_out$5 [0]
+        assign \output_cr \dec_cr_out [0]
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-    switch { $8 }
+    switch { $7 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
       case 1'1
         assign \xer_in 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-    switch { $10 }
+    switch { $9 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
       case 1'1
         assign \xer_out 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-    switch { $12 }
+    switch { $11 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
       case 1'1
         assign \trapaddr 13'0000001110000
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-    switch { $16 $14 }
+    switch { $15 $13 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
       case 2'-1
         assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-        assign \insn \opcode_in
+        assign \insn \dec_opcode_in
         assign \insn_type 7'0111111
         assign \fn_unit 11'00010000000
         assign \trapaddr 13'0000001110000
@@ -43664,7 +43622,7 @@ module \pdecode2
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
       case 2'1-
         assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-        assign \insn \opcode_in
+        assign \insn \dec_opcode_in
         assign \insn_type 7'0111111
         assign \fn_unit 11'00010000000
         assign \trapaddr 13'0000001110000
@@ -43673,7 +43631,7 @@ module \pdecode2
         assign \cia$2 \cia
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-    switch { $22 }
+    switch { $21 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
       case 1'1
         assign \fasto1 3'101
@@ -43682,7 +43640,7 @@ module \pdecode2
         assign \fasto2_ok 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-    switch { $24 }
+    switch { $23 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
       case 1'1
         assign \fast1 3'101
@@ -43696,83 +43654,83 @@ module \pdecode2
   wire width 32 \insn_in
   process $group_1
     assign \insn_in 32'00000000000000000000000000000000
-    assign \insn_in \opcode_in
+    assign \insn_in \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
-  wire width 32 \insn_in$26
+  wire width 32 \insn_in$25
   process $group_2
-    assign \insn_in$26 32'00000000000000000000000000000000
-    assign \insn_in$26 \opcode_in
+    assign \insn_in$25 32'00000000000000000000000000000000
+    assign \insn_in$25 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248"
-  wire width 32 \insn_in$27
+  wire width 32 \insn_in$26
   process $group_3
-    assign \insn_in$27 32'00000000000000000000000000000000
-    assign \insn_in$27 \opcode_in
+    assign \insn_in$26 32'00000000000000000000000000000000
+    assign \insn_in$26 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
-  wire width 32 \insn_in$28
+  wire width 32 \insn_in$27
   process $group_4
-    assign \insn_in$28 32'00000000000000000000000000000000
-    assign \insn_in$28 \opcode_in
+    assign \insn_in$27 32'00000000000000000000000000000000
+    assign \insn_in$27 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354"
-  wire width 32 \insn_in$29
+  wire width 32 \insn_in$28
   process $group_5
-    assign \insn_in$29 32'00000000000000000000000000000000
-    assign \insn_in$29 \opcode_in
+    assign \insn_in$28 32'00000000000000000000000000000000
+    assign \insn_in$28 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
-  wire width 32 \insn_in$30
+  wire width 32 \insn_in$29
   process $group_6
-    assign \insn_in$30 32'00000000000000000000000000000000
-    assign \insn_in$30 \opcode_in
+    assign \insn_in$29 32'00000000000000000000000000000000
+    assign \insn_in$29 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
-  wire width 32 \insn_in$31
+  wire width 32 \insn_in$30
   process $group_7
-    assign \insn_in$31 32'00000000000000000000000000000000
-    assign \insn_in$31 \opcode_in
+    assign \insn_in$30 32'00000000000000000000000000000000
+    assign \insn_in$30 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467"
-  wire width 32 \insn_in$32
+  wire width 32 \insn_in$31
   process $group_8
-    assign \insn_in$32 32'00000000000000000000000000000000
-    assign \insn_in$32 \opcode_in
+    assign \insn_in$31 32'00000000000000000000000000000000
+    assign \insn_in$31 \dec_opcode_in
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519"
-  wire width 32 \insn_in$33
+  wire width 32 \insn_in$32
   process $group_9
-    assign \insn_in$33 32'00000000000000000000000000000000
-    assign \insn_in$33 \opcode_in
+    assign \insn_in$32 32'00000000000000000000000000000000
+    assign \insn_in$32 \dec_opcode_in
     sync init
   end
   process $group_10
     assign \dec_a_sel_in 3'000
-    assign \dec_a_sel_in \in1_sel
+    assign \dec_a_sel_in \dec_in1_sel
     sync init
   end
   process $group_11
     assign \dec_b_sel_in 4'0000
-    assign \dec_b_sel_in \in2_sel
+    assign \dec_b_sel_in \dec_in2_sel
     sync init
   end
   process $group_12
     assign \dec_c_sel_in 2'00
-    assign \dec_c_sel_in \in3_sel
+    assign \dec_c_sel_in \dec_in3_sel
     sync init
   end
   process $group_13
     assign \dec_o_sel_in 2'00
-    assign \dec_o_sel_in \out_sel
+    assign \dec_o_sel_in \dec_out_sel
     sync init
   end
   attribute \enum_base_type "OutSel"
@@ -43784,7 +43742,7 @@ module \pdecode2
   wire width 2 \sel_in
   process $group_14
     assign \sel_in 2'00
-    assign \sel_in \out_sel
+    assign \sel_in \dec_out_sel
     sync init
   end
   process $group_15
@@ -43794,22 +43752,22 @@ module \pdecode2
   end
   process $group_16
     assign \dec_rc_sel_in 2'00
-    assign \dec_rc_sel_in \rc_sel
+    assign \dec_rc_sel_in \dec_rc_sel
     sync init
   end
   process $group_17
     assign \dec_oe_sel_in 2'00
-    assign \dec_oe_sel_in \rc_sel
+    assign \dec_oe_sel_in \dec_rc_sel
     sync init
   end
   process $group_18
     assign \dec_cr_in_sel_in 3'000
-    assign \dec_cr_in_sel_in \cr_in
+    assign \dec_cr_in_sel_in \dec_cr_in
     sync init
   end
   process $group_19
     assign \dec_cr_out_sel_in 3'000
-    assign \dec_cr_out_sel_in \cr_out$5
+    assign \dec_cr_out_sel_in \dec_cr_out
     sync init
   end
   process $group_20
@@ -43820,7 +43778,7 @@ module \pdecode2
   process $group_81
     assign \is_priv_insn 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38"
-    switch \internal_op
+    switch \dec_internal_op
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:40"
       attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70"
       case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110
@@ -50015,10 +49973,6 @@ module \alu0
   wire width 1 output 39 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 40 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 41 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 42 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_alu0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -50740,6 +50694,8 @@ module \alu0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -52034,6 +51990,8 @@ module \alu0
     assign \cu_rd__rel_o $145
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $147
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -52245,6 +52203,8 @@ module \alu0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p"
@@ -55858,10 +55818,6 @@ module \cr0
   wire width 1 output 24 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 output 25 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 26 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 27 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_cr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -56538,6 +56494,8 @@ module \cr0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -57487,6 +57445,8 @@ module \cr0
     assign \cu_rd__rel_o $119
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $121
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -57626,6 +57586,8 @@ module \cr0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p"
@@ -61126,10 +61088,6 @@ module \branch0
   wire width 1 output 24 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 25 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 26 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 27 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_branch0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -61806,6 +61764,8 @@ module \branch0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -62742,6 +62702,8 @@ module \branch0
     assign \cu_rd__rel_o $119
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $121
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -62881,6 +62843,8 @@ module \branch0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p"
@@ -66986,10 +66950,6 @@ module \trap0
   wire width 1 output 29 \msr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 31 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 32 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_trap0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -67677,6 +67637,8 @@ module \trap0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -68759,6 +68721,8 @@ module \trap0
     assign \cu_rd__rel_o $131
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $133
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -68970,6 +68934,8 @@ module \trap0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p"
@@ -81472,10 +81438,6 @@ module \logical0
   wire width 1 output 33 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 34 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 35 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_logical0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -82183,6 +82145,8 @@ module \logical0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -83249,6 +83213,8 @@ module \logical0
     assign \cu_rd__rel_o $123
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $125
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -83388,6 +83354,8 @@ module \logical0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p"
@@ -86745,10 +86713,6 @@ module \spr0
   wire width 1 output 29 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 30 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 31 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 32 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_spr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -87434,6 +87398,8 @@ module \spr0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $60
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -88618,6 +88584,8 @@ module \spr0
     assign \cu_rd__rel_o $146
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $148
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -88865,6 +88833,8 @@ module \spr0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p"
@@ -97886,10 +97856,6 @@ module \mul0
   wire width 1 output 33 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 1 output 34 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 35 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_mul0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -98591,6 +98557,8 @@ module \mul0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -99734,6 +99702,8 @@ module \mul0
     assign \cu_rd__rel_o $134
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $136
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -99909,6 +99879,8 @@ module \mul0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p"
@@ -105806,10 +105778,6 @@ module \shiftrot0
   wire width 1 output 33 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 output 34 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 35 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 36 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_shift_rot0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -106514,6 +106482,8 @@ module \shiftrot0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
   wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
   wire width 1 $56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
@@ -107572,6 +107542,8 @@ module \shiftrot0
     assign \cu_rd__rel_o $120
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
   wire width 1 $122
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
@@ -107711,6 +107683,8 @@ module \shiftrot0
     end
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
@@ -109166,13 +109140,13 @@ attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
 module \ldst0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \ad__go_i
+  wire width 1 input 0 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \ad__rel_o
+  wire width 1 output 1 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \st__go_i
+  wire width 1 input 2 \cu_st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \st__rel_o
+  wire width 1 output 3 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 4 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
@@ -109307,36 +109281,28 @@ module \ldst0
   wire width 64 output 30 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 output 31 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 32 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
-  wire width 1 output 33 \load_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
-  wire width 1 output 34 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 35 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 36 \ldst_port0_is_ld_i
+  wire width 1 output 32 \ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 37 \ldst_port0_is_st_i
+  wire width 1 output 33 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 38 \ldst_port0_data_len
+  wire width 4 output 34 \ldst_port0_data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 39 \ldst_port0_addr_i
+  wire width 96 output 35 \ldst_port0_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 40 \ldst_port0_addr_i_ok
+  wire width 1 output 36 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 41 \ldst_port0_addr_exc_o
+  wire width 1 input 37 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 input 42 \ldst_port0_addr_ok_o
+  wire width 1 input 38 \ldst_port0_addr_ok_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 43 \ldst_port0_ld_data_o
+  wire width 64 input 39 \ldst_port0_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 44 \ldst_port0_ld_data_o_ok
+  wire width 1 input 40 \ldst_port0_ld_data_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 45 \ldst_port0_st_data_i
+  wire width 64 output 41 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 46 \ldst_port0_st_data_i_ok
+  wire width 1 output 42 \ldst_port0_st_data_i_ok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \opc_l_s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -109487,6 +109453,8 @@ module \ldst0
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
   wire width 1 \reset_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
   wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
@@ -109578,7 +109546,7 @@ module \ldst0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__go_i
+    connect \A \cu_st__go_i
     connect \B \cu_go_die_i
     connect \Y $9
   end
@@ -109618,7 +109586,7 @@ module \ldst0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ad__go_i
+    connect \A \cu_ad__go_i
     connect \B \cu_go_die_i
     connect \Y $13
   end
@@ -109633,7 +109601,7 @@ module \ldst0
   wire width 1 \p_st_go$next
   process $group_7
     assign \p_st_go$next \p_st_go
-    assign \p_st_go$next \st__go_i
+    assign \p_st_go$next \cu_st__go_i
     sync init
       update \p_st_go 1'0
     sync posedge \clk
@@ -110473,6 +110441,8 @@ module \ldst0
     assign \op_is_ld $55
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
+  wire width 1 \load_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
   wire width 1 $57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
@@ -110483,7 +110453,7 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_ld
-    connect \B \ad__go_i
+    connect \B \cu_ad__go_i
     connect \Y $57
   end
   process $group_72
@@ -110491,6 +110461,8 @@ module \ldst0
     assign \load_mem_o $57
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
+  wire width 1 \stwd_mem_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
   wire width 1 $59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
@@ -110501,7 +110473,7 @@ module \ldst0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \op_is_st
-    connect \B \st__go_i
+    connect \B \cu_st__go_i
     connect \Y $59
   end
   process $group_73
@@ -110735,8 +110707,8 @@ module \ldst0
     connect \Y $89
   end
   process $group_81
-    assign \ad__rel_o 1'0
-    assign \ad__rel_o $89
+    assign \cu_ad__rel_o 1'0
+    assign \cu_ad__rel_o $89
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
@@ -110778,6 +110750,8 @@ module \ldst0
     connect \B \op_is_st
     connect \Y $95
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
   wire width 1 $97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
@@ -110792,8 +110766,8 @@ module \ldst0
     connect \Y $97
   end
   process $group_82
-    assign \st__rel_o 1'0
-    assign \st__rel_o $97
+    assign \cu_st__rel_o 1'0
+    assign \cu_st__rel_o $97
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
@@ -110943,7 +110917,7 @@ module \ldst0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__go_i
+    connect \A \cu_st__go_i
     connect \B \p_st_go
     connect \Y $119
   end
@@ -111015,7 +110989,7 @@ module \ldst0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \st__rel_o
+    connect \A \cu_st__rel_o
     connect \B \cu_wr__rel_o [0]
     connect \Y $130
   end
@@ -111382,21 +111356,23 @@ module \ldst0
   end
   process $group_104
     assign \ldst_port0_st_data_i_ok 1'0
-    assign \ldst_port0_st_data_i_ok \st__go_i
+    assign \ldst_port0_st_data_i_ok \cu_st__go_i
     sync init
   end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus"
 module \fus
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \ad__go_i
+  wire width 1 input 0 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \ad__rel_o
+  wire width 1 output 1 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \st__go_i
+  wire width 1 input 2 \cu_st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \st__rel_o
+  wire width 1 output 3 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 4 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
@@ -112709,68 +112685,28 @@ module \fus
   wire width 1 output 274 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 output 275 \dest2_o$132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 276 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 277 \cu_shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 278 \cu_go_die_i$133
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 279 \cu_shadown_i$134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 280 \cu_go_die_i$135
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 281 \cu_shadown_i$136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 282 \cu_go_die_i$137
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 283 \cu_shadown_i$138
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 284 \cu_go_die_i$139
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 285 \cu_shadown_i$140
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 286 \cu_go_die_i$141
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 287 \cu_shadown_i$142
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 288 \cu_go_die_i$143
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 289 \cu_shadown_i$144
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 290 \cu_go_die_i$145
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 291 \cu_shadown_i$146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 292 \cu_go_die_i$147
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
-  wire width 1 output 293 \load_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
-  wire width 1 output 294 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 295 \cu_shadown_i$148
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 296 \ldst_port0_is_ld_i
+  wire width 1 output 276 \ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 297 \ldst_port0_is_st_i
+  wire width 1 output 277 \ldst_port0_is_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 298 \ldst_port0_data_len
+  wire width 4 output 278 \ldst_port0_data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 299 \ldst_port0_addr_i
+  wire width 96 output 279 \ldst_port0_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 300 \ldst_port0_addr_i_ok
+  wire width 1 output 280 \ldst_port0_addr_i_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 301 \ldst_port0_addr_exc_o
+  wire width 1 input 281 \ldst_port0_addr_exc_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 input 302 \ldst_port0_addr_ok_o
+  wire width 1 input 282 \ldst_port0_addr_ok_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 303 \ldst_port0_ld_data_o
+  wire width 64 input 283 \ldst_port0_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 304 \ldst_port0_ld_data_o_ok
+  wire width 1 input 284 \ldst_port0_ld_data_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 305 \ldst_port0_st_data_i
+  wire width 64 output 285 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 306 \ldst_port0_st_data_i_ok
+  wire width 1 output 286 \ldst_port0_st_data_i_ok
   cell \alu0 \alu0
     connect \rst \rst
     connect \clk \clk
@@ -112813,8 +112749,6 @@ module \fus
     connect \dest4_o \dest4_o
     connect \xer_so_ok \xer_so_ok
     connect \dest5_o \dest5_o$115
-    connect \cu_go_die_i \cu_go_die_i
-    connect \cu_shadown_i \cu_shadown_i
   end
   cell \cr0 \cr0
     connect \rst \rst
@@ -112843,8 +112777,6 @@ module \fus
     connect \dest2_o \dest2_o
     connect \cr_a_ok \cr_a_ok$96
     connect \dest3_o \dest3_o
-    connect \cu_go_die_i \cu_go_die_i$133
-    connect \cu_shadown_i \cu_shadown_i$134
   end
   cell \branch0 \branch0
     connect \rst \rst
@@ -112873,8 +112805,6 @@ module \fus
     connect \dest2_o \dest2_o$126
     connect \nia_ok \nia_ok
     connect \dest3_o \dest3_o$129
-    connect \cu_go_die_i \cu_go_die_i$135
-    connect \cu_shadown_i \cu_shadown_i$136
   end
   cell \trap0 \trap0
     connect \rst \rst
@@ -112908,8 +112838,6 @@ module \fus
     connect \dest4_o \dest4_o$130
     connect \msr_ok \msr_ok
     connect \dest5_o \dest5_o$131
-    connect \cu_go_die_i \cu_go_die_i$137
-    connect \cu_shadown_i \cu_shadown_i$138
   end
   cell \logical0 \logical0
     connect \rst \rst
@@ -112947,8 +112875,6 @@ module \fus
     connect \dest2_o \dest2_o$101
     connect \xer_ca_ok \xer_ca_ok$104
     connect \dest3_o \dest3_o$108
-    connect \cu_go_die_i \cu_go_die_i$139
-    connect \cu_shadown_i \cu_shadown_i$140
   end
   cell \spr0 \spr0
     connect \rst \rst
@@ -112982,8 +112908,6 @@ module \fus
     connect \dest3_o \dest3_o$124
     connect \spr1_ok \spr1_ok
     connect \dest2_o \dest2_o$132
-    connect \cu_go_die_i \cu_go_die_i$141
-    connect \cu_shadown_i \cu_shadown_i$142
   end
   cell \mul0 \mul0
     connect \rst \rst
@@ -113021,8 +112945,6 @@ module \fus
     connect \dest3_o \dest3_o$112
     connect \xer_so_ok \xer_so_ok$114
     connect \dest4_o \dest4_o$117
-    connect \cu_go_die_i \cu_go_die_i$143
-    connect \cu_shadown_i \cu_shadown_i$144
   end
   cell \shiftrot0 \shiftrot0
     connect \rst \rst
@@ -113059,14 +112981,12 @@ module \fus
     connect \dest2_o \dest2_o$103
     connect \xer_ca_ok \xer_ca_ok$106
     connect \dest3_o \dest3_o$109
-    connect \cu_go_die_i \cu_go_die_i$145
-    connect \cu_shadown_i \cu_shadown_i$146
   end
   cell \ldst0 \ldst0
-    connect \ad__go_i \ad__go_i
-    connect \ad__rel_o \ad__rel_o
-    connect \st__go_i \st__go_i
-    connect \st__rel_o \st__rel_o
+    connect \cu_ad__go_i \cu_ad__go_i
+    connect \cu_ad__rel_o \cu_ad__rel_o
+    connect \cu_st__go_i \cu_st__go_i
+    connect \cu_st__rel_o \cu_st__rel_o
     connect \rst \rst
     connect \clk \clk
     connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
@@ -113095,10 +113015,6 @@ module \fus
     connect \cu_wr__go_i \cu_wr__go_i$89
     connect \o \o
     connect \ea \ea
-    connect \cu_go_die_i \cu_go_die_i$147
-    connect \load_mem_o \load_mem_o
-    connect \stwd_mem_o \stwd_mem_o
-    connect \cu_shadown_i \cu_shadown_i$148
     connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
     connect \ldst_port0_is_st_i \ldst_port0_is_st_i
     connect \ldst_port0_data_len \ldst_port0_data_len
@@ -115390,12 +115306,6 @@ module \l0$106
   wire width 64 output 23 \ldst_port0_st_data_i$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
   wire width 1 input 24 \ldst_port0_addr_exc_o$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 output 25 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 26 \ldst_port0_go_die_i$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 27 \ldst_port0_busy_o$13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \idx_l_q_idx_l
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -115434,9 +115344,9 @@ module \l0$106
     connect \n \pick_n
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
-  wire width 1 $14
+  wire width 1 $12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
-  cell $or $15
+  cell $or $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -115444,67 +115354,67 @@ module \l0$106
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_is_ld_i
     connect \B \ldst_port0_is_st_i
-    connect \Y $14
+    connect \Y $12
   end
   process $group_0
     assign \pick_i 1'0
-    assign \pick_i { $14 }
+    assign \pick_i { $12 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 1 $16
+  wire width 1 $14
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 1 \idx_l$17
+  wire width 1 \idx_l$15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 1 \idx_l$17$next
+  wire width 1 \idx_l$15$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 1 $18
+  wire width 1 $16
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $19
+  cell $mux $17
     parameter \WIDTH 1
-    connect \A \idx_l$17
+    connect \A \idx_l$15
     connect \B \pick_o
     connect \S \idx_l_q_idx_l
-    connect \Y $18
+    connect \Y $16
   end
-  connect $16 $18
+  connect $14 $16
   process $group_1
     assign { } 0'0
     assign { } {}
     sync init
   end
   process $group_2
-    assign \idx_l$17$next \idx_l$17
+    assign \idx_l$15$next \idx_l$15
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \idx_l_q_idx_l }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \idx_l$17$next \pick_o
+        assign \idx_l$15$next \pick_o
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \idx_l$17$next 1'0
+        assign \idx_l$15$next 1'0
     end
     sync init
-      update \idx_l$17 1'0
+      update \idx_l$15 1'0
     sync posedge \clk
-      update \idx_l$17 \idx_l$17$next
+      update \idx_l$15 \idx_l$15$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-  wire width 1 $20
+  wire width 1 $18
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-  cell $not $21
+  cell $not $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pick_n
-    connect \Y $20
+    connect \Y $18
   end
   process $group_3
     assign \idx_l_s_idx_l 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-    switch { $20 }
+    switch { $18 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
       case 1'1
         assign \idx_l_s_idx_l 1'1
@@ -115512,14 +115422,14 @@ module \l0$106
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-  wire width 1 $22
+  wire width 1 $20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-  cell $not $23
+  cell $not $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ldst_port0_busy_o
-    connect \Y $22
+    connect \Y $20
   end
   process $group_4
     assign \reset_l_s_reset 1'0
@@ -115529,7 +115439,7 @@ module \l0$106
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
       case 1'1
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-        switch { $22 }
+        switch { $20 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
           case 1'1
             assign \reset_l_s_reset 1'1
@@ -115590,6 +115500,10 @@ module \l0$106
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+  wire width 1 \ldst_port0_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+  wire width 1 \ldst_port0_go_die_i$22
   process $group_9
     assign \ldst_port0_go_die_i 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
@@ -115599,16 +115513,16 @@ module \l0$106
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118"
         switch { }
           case 0'
-            assign \ldst_port0_go_die_i \ldst_port0_go_die_i$12
+            assign \ldst_port0_go_die_i \ldst_port0_go_die_i$22
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
-  wire width 96 $24
+  wire width 96 $23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
-  wire width 96 $25
-  connect $25 \ldst_port0_addr_i
+  wire width 96 $24
+  connect $24 \ldst_port0_addr_i
   process $group_10
     assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
@@ -115618,7 +115532,7 @@ module \l0$106
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
         switch { }
           case 0'
-            assign \ldst_port0_addr_i$4 $25 [47:0]
+            assign \ldst_port0_addr_i$4 $24 [47:0]
         end
     end
     sync init
@@ -115667,8 +115581,10 @@ module \l0$106
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 \ldst_port0_busy_o$25
   process $group_16
-    assign \ldst_port0_busy_o$13 1'0
+    assign \ldst_port0_busy_o$25 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
     switch { \idx_l_q_idx_l }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
@@ -115676,7 +115592,7 @@ module \l0$106
         attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
         switch { }
           case 0'
-            assign \ldst_port0_busy_o$13 \ldst_port0_busy_o
+            assign \ldst_port0_busy_o$25 \ldst_port0_busy_o
         end
     end
     sync init
@@ -115731,6 +115647,7 @@ module \l0$106
     end
     sync init
   end
+  connect \ldst_port0_go_die_i$22 1'0
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem"
@@ -116636,104 +116553,98 @@ module \l0
   wire width 64 input 11 \ldst_port0_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 12 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 13 \ldst_port0_is_ld_i$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 14 \ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 15 \ldst_port0_is_st_i$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 16 \ldst_port0_data_len$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 output 17 \ldst_port0_addr_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 18 \ldst_port0_addr_i_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 19 \x_mask_i
+  wire width 8 output 13 \x_mask_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 20 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 21 \ldst_port0_addr_ok_o$6
+  wire width 48 output 14 \x_addr_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 22 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 23 \ldst_port0_ld_data_o$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 24 \ldst_port0_ld_data_o_ok$8
+  wire width 64 output 15 \m_ld_data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 25 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 26 \ldst_port0_st_data_i_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 27 \ldst_port0_st_data_i$10
+  wire width 1 output 16 \x_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 28 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 29 \ldst_port0_addr_exc_o$11
+  wire width 64 output 17 \x_st_data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 30 \x_ld_i
+  wire width 1 output 18 \x_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 31 \x_st_i
+  wire width 1 output 19 \x_st_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 32 \m_valid_i
+  wire width 1 output 20 \m_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 33 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 output 34 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 35 \ldst_port0_go_die_i$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 36 \ldst_port0_busy_o$13
+  wire width 1 output 21 \x_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 37 \dbus__cyc
+  wire width 1 output 22 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 38 \x_stall_i
+  wire width 1 input 23 \x_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 39 \dbus__ack
+  wire width 1 input 24 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 40 \dbus__err
+  wire width 1 input 25 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 41 \dbus__stb
+  wire width 1 output 26 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 42 \dbus__dat_r
+  wire width 64 input 27 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 43 \dbus__adr
+  wire width 45 output 28 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 44 \dbus__sel
+  wire width 8 output 29 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 45 \dbus__we
+  wire width 1 output 30 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 46 \dbus__dat_w
+  wire width 64 output 31 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 47 \m_stall_i
+  wire width 1 input 32 \m_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 48 \m_load_err_o
+  wire width 1 output 33 \m_load_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 49 \m_store_err_o
+  wire width 1 output 34 \m_store_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 50 \m_badaddr_o
+  wire width 45 output 35 \m_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 51 \m_busy_o
+  wire width 1 output 36 \m_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 \pimem_ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 \pimem_ldst_port0_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 \pimem_ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 \pimem_ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 48 \pimem_ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 \pimem_ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pimem_ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pimem_ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 \pimem_ldst_port0_addr_exc_o
   cell \pimem \pimem
     connect \rst \rst
     connect \clk \clk
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$1
-    connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i$2
-    connect \ldst_port0_data_len \ldst_port0_data_len$3
-    connect \ldst_port0_addr_i \ldst_port0_addr_i$4
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$5
+    connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
+    connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \pimem_ldst_port0_data_len
+    connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
     connect \x_mask_i \x_mask_i
     connect \x_addr_i \x_addr_i
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
+    connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o
     connect \m_ld_data_o \m_ld_data_o
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$7
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$8
+    connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
     connect \x_busy_o \x_busy_o
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$9
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i$10
+    connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
+    connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
     connect \x_st_data_i \x_st_data_i
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
+    connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
     connect \x_ld_i \x_ld_i
     connect \x_st_i \x_st_i
     connect \m_valid_i \m_valid_i
@@ -116753,21 +116664,18 @@ module \l0
     connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
     connect \ldst_port0_st_data_i \ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
-    connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$1
-    connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$2
-    connect \ldst_port0_data_len$3 \ldst_port0_data_len$3
-    connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$4
-    connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$5
-    connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$6
-    connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$7
-    connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$8
-    connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$9
-    connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$10
-    connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$11
-    connect \ldst_port0_go_die_i \ldst_port0_go_die_i
-    connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$12
-    connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$13
+    connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
+    connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len
+    connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_ok_o$6 \pimem_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o$7 \pimem_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok$8 \pimem_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i_ok$9 \pimem_ldst_port0_st_data_i_ok
+    connect \ldst_port0_st_data_i$10 \pimem_ldst_port0_st_data_i
+    connect \ldst_port0_addr_exc_o$11 \pimem_ldst_port0_addr_exc_o
   end
   cell \lsmem \lsmem
     connect \rst \rst
@@ -116797,6 +116705,7 @@ module \l0
     connect \m_badaddr_o \m_badaddr_o
     connect \m_busy_o \m_busy_o
   end
+  connect \pimem_ldst_port0_addr_exc_o 1'0
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
@@ -146906,13 +146815,13 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 input 4 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 5 \ad__go_i
+  wire width 1 input 5 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 6 \ad__rel_o
+  wire width 1 output 6 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 7 \st__go_i
+  wire width 1 input 7 \cu_st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 8 \st__rel_o
+  wire width 1 output 8 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 input 9 \cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -147016,6 +146925,54 @@ module \core
   wire width 1 input 22 \rst
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
   wire width 1 input 23 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 output 24 \x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 output 25 \x_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 output 26 \m_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 output 27 \x_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 output 28 \x_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 output 29 \x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 output 30 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 output 31 \m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 output 32 \x_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 33 \dbus__cyc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+  wire width 1 input 34 \x_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 35 \dbus__ack
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 36 \dbus__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 37 \dbus__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 input 38 \dbus__dat_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 45 output 39 \dbus__adr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 8 output 40 \dbus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 41 \dbus__we
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 output 42 \dbus__dat_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+  wire width 1 input 43 \m_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 output 44 \m_load_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 output 45 \m_store_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 output 46 \m_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+  wire width 1 output 47 \m_busy_o
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147029,7 +146986,405 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40"
-  wire width 11 output 24 \fn_unit
+  wire width 11 \pdecode2_fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pdecode2_imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+  wire width 1 \pdecode2_invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+  wire width 1 \pdecode2_zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
+  wire width 1 \pdecode2_invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
+  wire width 1 \pdecode2_write_cr0
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+  wire width 2 \pdecode2_input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+  wire width 1 \pdecode2_output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+  wire width 1 \pdecode2_is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+  wire width 1 \pdecode2_is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
+  wire width 4 \pdecode2_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+  wire width 32 \pdecode2_insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_reg1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_reg2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+  wire width 1 \pdecode2_xer_in
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+  wire width 1 \pdecode2_read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
+  wire width 1 \pdecode2_write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_cr_in1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_cr_in2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_cr_in2_ok$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
+  wire width 64 \pdecode2_cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
+  wire width 1 \pdecode2_lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_fast1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_fast2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+  wire width 64 \pdecode2_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+  wire width 5 \pdecode2_traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+  wire width 13 \pdecode2_trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_spr1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+  wire width 1 \pdecode2_input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+  wire width 1 \pdecode2_output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pdecode2_reg3_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+  wire width 1 \pdecode2_byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+  wire width 1 \pdecode2_sign_extend
+  attribute \enum_base_type "LDSTMode"
+  attribute \enum_value_00 "NONE"
+  attribute \enum_value_01 "update"
+  attribute \enum_value_10 "cix"
+  attribute \enum_value_11 "cx"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
+  wire width 2 \pdecode2_ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 \pdecode2_reg1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 \pdecode2_reg2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 \pdecode2_reg3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_cr_in1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_cr_in2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_cr_in2$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_fast1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_fast2
+  attribute \enum_base_type "SPR"
+  attribute \enum_value_0000000001 "XER"
+  attribute \enum_value_0000000011 "DSCR"
+  attribute \enum_value_0000001000 "LR"
+  attribute \enum_value_0000001001 "CTR"
+  attribute \enum_value_0000001101 "AMR"
+  attribute \enum_value_0000010001 "DSCR_priv"
+  attribute \enum_value_0000010010 "DSISR"
+  attribute \enum_value_0000010011 "DAR"
+  attribute \enum_value_0000010110 "DEC"
+  attribute \enum_value_0000011010 "SRR0"
+  attribute \enum_value_0000011011 "SRR1"
+  attribute \enum_value_0000011100 "CFAR"
+  attribute \enum_value_0000011101 "AMR_priv"
+  attribute \enum_value_0000110000 "PIDR"
+  attribute \enum_value_0000111101 "IAMR"
+  attribute \enum_value_0010000000 "TFHAR"
+  attribute \enum_value_0010000001 "TFIAR"
+  attribute \enum_value_0010000010 "TEXASR"
+  attribute \enum_value_0010000011 "TEXASRU"
+  attribute \enum_value_0010001000 "CTRL"
+  attribute \enum_value_0010010000 "TIDR"
+  attribute \enum_value_0010011000 "CTRL_priv"
+  attribute \enum_value_0010011001 "FSCR"
+  attribute \enum_value_0010011101 "UAMOR"
+  attribute \enum_value_0010011110 "GSR"
+  attribute \enum_value_0010011111 "PSPB"
+  attribute \enum_value_0010110000 "DPDES"
+  attribute \enum_value_0010110100 "DAWR0"
+  attribute \enum_value_0010111010 "RPR"
+  attribute \enum_value_0010111011 "CIABR"
+  attribute \enum_value_0010111100 "DAWRX0"
+  attribute \enum_value_0010111110 "HFSCR"
+  attribute \enum_value_0100000000 "VRSAVE"
+  attribute \enum_value_0100000011 "SPRG3"
+  attribute \enum_value_0100001100 "TB"
+  attribute \enum_value_0100001101 "TBU"
+  attribute \enum_value_0100010000 "SPRG0_priv"
+  attribute \enum_value_0100010001 "SPRG1_priv"
+  attribute \enum_value_0100010010 "SPRG2_priv"
+  attribute \enum_value_0100010011 "SPRG3_priv"
+  attribute \enum_value_0100011011 "CIR"
+  attribute \enum_value_0100011100 "TBL"
+  attribute \enum_value_0100011101 "TBU_hypv"
+  attribute \enum_value_0100011110 "TBU40"
+  attribute \enum_value_0100011111 "PVR"
+  attribute \enum_value_0100110000 "HSPRG0"
+  attribute \enum_value_0100110001 "HSPRG1"
+  attribute \enum_value_0100110010 "HDSISR"
+  attribute \enum_value_0100110011 "HDAR"
+  attribute \enum_value_0100110100 "SPURR"
+  attribute \enum_value_0100110101 "PURR"
+  attribute \enum_value_0100110110 "HDEC"
+  attribute \enum_value_0100111001 "HRMOR"
+  attribute \enum_value_0100111010 "HSRR0"
+  attribute \enum_value_0100111011 "HSRR1"
+  attribute \enum_value_0100111110 "LPCR"
+  attribute \enum_value_0100111111 "LPIDR"
+  attribute \enum_value_0101010000 "HMER"
+  attribute \enum_value_0101010001 "HMEER"
+  attribute \enum_value_0101010010 "PCR"
+  attribute \enum_value_0101010011 "HEIR"
+  attribute \enum_value_0101011101 "AMOR"
+  attribute \enum_value_0110111110 "TIR"
+  attribute \enum_value_0111010000 "PTCR"
+  attribute \enum_value_1100000000 "SIER"
+  attribute \enum_value_1100000001 "MMCR2"
+  attribute \enum_value_1100000010 "MMCRA"
+  attribute \enum_value_1100000011 "PMC1"
+  attribute \enum_value_1100000100 "PMC2"
+  attribute \enum_value_1100000101 "PMC3"
+  attribute \enum_value_1100000110 "PMC4"
+  attribute \enum_value_1100000111 "PMC5"
+  attribute \enum_value_1100001000 "PMC6"
+  attribute \enum_value_1100001011 "MMCR0"
+  attribute \enum_value_1100001100 "SIAR"
+  attribute \enum_value_1100001101 "SDAR"
+  attribute \enum_value_1100001110 "MMCR1"
+  attribute \enum_value_1100010000 "SIER_priv"
+  attribute \enum_value_1100010001 "MMCR2_priv"
+  attribute \enum_value_1100010010 "MMCRA_priv"
+  attribute \enum_value_1100010011 "PMC1_priv"
+  attribute \enum_value_1100010100 "PMC2_priv"
+  attribute \enum_value_1100010101 "PMC3_priv"
+  attribute \enum_value_1100010110 "PMC4_priv"
+  attribute \enum_value_1100010111 "PMC5_priv"
+  attribute \enum_value_1100011000 "PMC6_priv"
+  attribute \enum_value_1100011011 "MMCR0_priv"
+  attribute \enum_value_1100011100 "SIAR_priv"
+  attribute \enum_value_1100011101 "SDAR_priv"
+  attribute \enum_value_1100011110 "MMCR1_priv"
+  attribute \enum_value_1100100000 "BESCRS"
+  attribute \enum_value_1100100001 "BESCRSU"
+  attribute \enum_value_1100100010 "BESCRR"
+  attribute \enum_value_1100100011 "BESCRRU"
+  attribute \enum_value_1100100100 "EBBHR"
+  attribute \enum_value_1100100101 "EBBRR"
+  attribute \enum_value_1100100110 "BESCR"
+  attribute \enum_value_1100101000 "reserved808"
+  attribute \enum_value_1100101001 "reserved809"
+  attribute \enum_value_1100101010 "reserved810"
+  attribute \enum_value_1100101011 "reserved811"
+  attribute \enum_value_1100101111 "TAR"
+  attribute \enum_value_1100110000 "ASDR"
+  attribute \enum_value_1100110111 "PSSCR"
+  attribute \enum_value_1101010000 "IC"
+  attribute \enum_value_1101010001 "VTB"
+  attribute \enum_value_1101010111 "PSSCR_hypv"
+  attribute \enum_value_1110000000 "PPR"
+  attribute \enum_value_1110000010 "PPR32"
+  attribute \enum_value_1111111111 "PIR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 10 \pdecode2_spr1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 \pdecode2_rego
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 5 \pdecode2_ea
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_cr_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_fasto1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 3 \pdecode2_fasto2
+  attribute \enum_base_type "SPR"
+  attribute \enum_value_0000000001 "XER"
+  attribute \enum_value_0000000011 "DSCR"
+  attribute \enum_value_0000001000 "LR"
+  attribute \enum_value_0000001001 "CTR"
+  attribute \enum_value_0000001101 "AMR"
+  attribute \enum_value_0000010001 "DSCR_priv"
+  attribute \enum_value_0000010010 "DSISR"
+  attribute \enum_value_0000010011 "DAR"
+  attribute \enum_value_0000010110 "DEC"
+  attribute \enum_value_0000011010 "SRR0"
+  attribute \enum_value_0000011011 "SRR1"
+  attribute \enum_value_0000011100 "CFAR"
+  attribute \enum_value_0000011101 "AMR_priv"
+  attribute \enum_value_0000110000 "PIDR"
+  attribute \enum_value_0000111101 "IAMR"
+  attribute \enum_value_0010000000 "TFHAR"
+  attribute \enum_value_0010000001 "TFIAR"
+  attribute \enum_value_0010000010 "TEXASR"
+  attribute \enum_value_0010000011 "TEXASRU"
+  attribute \enum_value_0010001000 "CTRL"
+  attribute \enum_value_0010010000 "TIDR"
+  attribute \enum_value_0010011000 "CTRL_priv"
+  attribute \enum_value_0010011001 "FSCR"
+  attribute \enum_value_0010011101 "UAMOR"
+  attribute \enum_value_0010011110 "GSR"
+  attribute \enum_value_0010011111 "PSPB"
+  attribute \enum_value_0010110000 "DPDES"
+  attribute \enum_value_0010110100 "DAWR0"
+  attribute \enum_value_0010111010 "RPR"
+  attribute \enum_value_0010111011 "CIABR"
+  attribute \enum_value_0010111100 "DAWRX0"
+  attribute \enum_value_0010111110 "HFSCR"
+  attribute \enum_value_0100000000 "VRSAVE"
+  attribute \enum_value_0100000011 "SPRG3"
+  attribute \enum_value_0100001100 "TB"
+  attribute \enum_value_0100001101 "TBU"
+  attribute \enum_value_0100010000 "SPRG0_priv"
+  attribute \enum_value_0100010001 "SPRG1_priv"
+  attribute \enum_value_0100010010 "SPRG2_priv"
+  attribute \enum_value_0100010011 "SPRG3_priv"
+  attribute \enum_value_0100011011 "CIR"
+  attribute \enum_value_0100011100 "TBL"
+  attribute \enum_value_0100011101 "TBU_hypv"
+  attribute \enum_value_0100011110 "TBU40"
+  attribute \enum_value_0100011111 "PVR"
+  attribute \enum_value_0100110000 "HSPRG0"
+  attribute \enum_value_0100110001 "HSPRG1"
+  attribute \enum_value_0100110010 "HDSISR"
+  attribute \enum_value_0100110011 "HDAR"
+  attribute \enum_value_0100110100 "SPURR"
+  attribute \enum_value_0100110101 "PURR"
+  attribute \enum_value_0100110110 "HDEC"
+  attribute \enum_value_0100111001 "HRMOR"
+  attribute \enum_value_0100111010 "HSRR0"
+  attribute \enum_value_0100111011 "HSRR1"
+  attribute \enum_value_0100111110 "LPCR"
+  attribute \enum_value_0100111111 "LPIDR"
+  attribute \enum_value_0101010000 "HMER"
+  attribute \enum_value_0101010001 "HMEER"
+  attribute \enum_value_0101010010 "PCR"
+  attribute \enum_value_0101010011 "HEIR"
+  attribute \enum_value_0101011101 "AMOR"
+  attribute \enum_value_0110111110 "TIR"
+  attribute \enum_value_0111010000 "PTCR"
+  attribute \enum_value_1100000000 "SIER"
+  attribute \enum_value_1100000001 "MMCR2"
+  attribute \enum_value_1100000010 "MMCRA"
+  attribute \enum_value_1100000011 "PMC1"
+  attribute \enum_value_1100000100 "PMC2"
+  attribute \enum_value_1100000101 "PMC3"
+  attribute \enum_value_1100000110 "PMC4"
+  attribute \enum_value_1100000111 "PMC5"
+  attribute \enum_value_1100001000 "PMC6"
+  attribute \enum_value_1100001011 "MMCR0"
+  attribute \enum_value_1100001100 "SIAR"
+  attribute \enum_value_1100001101 "SDAR"
+  attribute \enum_value_1100001110 "MMCR1"
+  attribute \enum_value_1100010000 "SIER_priv"
+  attribute \enum_value_1100010001 "MMCR2_priv"
+  attribute \enum_value_1100010010 "MMCRA_priv"
+  attribute \enum_value_1100010011 "PMC1_priv"
+  attribute \enum_value_1100010100 "PMC2_priv"
+  attribute \enum_value_1100010101 "PMC3_priv"
+  attribute \enum_value_1100010110 "PMC4_priv"
+  attribute \enum_value_1100010111 "PMC5_priv"
+  attribute \enum_value_1100011000 "PMC6_priv"
+  attribute \enum_value_1100011011 "MMCR0_priv"
+  attribute \enum_value_1100011100 "SIAR_priv"
+  attribute \enum_value_1100011101 "SDAR_priv"
+  attribute \enum_value_1100011110 "MMCR1_priv"
+  attribute \enum_value_1100100000 "BESCRS"
+  attribute \enum_value_1100100001 "BESCRSU"
+  attribute \enum_value_1100100010 "BESCRR"
+  attribute \enum_value_1100100011 "BESCRRU"
+  attribute \enum_value_1100100100 "EBBHR"
+  attribute \enum_value_1100100101 "EBBRR"
+  attribute \enum_value_1100100110 "BESCR"
+  attribute \enum_value_1100101000 "reserved808"
+  attribute \enum_value_1100101001 "reserved809"
+  attribute \enum_value_1100101010 "reserved810"
+  attribute \enum_value_1100101011 "reserved811"
+  attribute \enum_value_1100101111 "TAR"
+  attribute \enum_value_1100110000 "ASDR"
+  attribute \enum_value_1100110111 "PSSCR"
+  attribute \enum_value_1101010000 "IC"
+  attribute \enum_value_1101010001 "VTB"
+  attribute \enum_value_1101010111 "PSSCR_hypv"
+  attribute \enum_value_1110000000 "PPR"
+  attribute \enum_value_1110000010 "PPR32"
+  attribute \enum_value_1111111111 "PIR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 10 \pdecode2_spro
+  cell \pdecode2 \pdecode2
+    connect \bigendian \bigendian
+    connect \raw_opcode_in \raw_opcode_in
+    connect \msr \msr
+    connect \cia \cia
+    connect \insn_type \insn_type
+    connect \fn_unit \pdecode2_fn_unit
+    connect \imm \pdecode2_imm
+    connect \imm_ok \pdecode2_imm_ok
+    connect \rc \pdecode2_rc
+    connect \rc_ok \pdecode2_rc_ok
+    connect \oe \pdecode2_oe
+    connect \oe_ok \pdecode2_oe_ok
+    connect \invert_a \pdecode2_invert_a
+    connect \zero_a \pdecode2_zero_a
+    connect \invert_out \pdecode2_invert_out
+    connect \write_cr0 \pdecode2_write_cr0
+    connect \input_carry \pdecode2_input_carry
+    connect \output_carry \pdecode2_output_carry
+    connect \is_32bit \pdecode2_is_32bit
+    connect \is_signed \pdecode2_is_signed
+    connect \data_len \pdecode2_data_len
+    connect \insn \pdecode2_insn
+    connect \reg1_ok \pdecode2_reg1_ok
+    connect \reg2_ok \pdecode2_reg2_ok
+    connect \xer_in \pdecode2_xer_in
+    connect \read_cr_whole \pdecode2_read_cr_whole
+    connect \write_cr_whole \pdecode2_write_cr_whole
+    connect \cr_in1_ok \pdecode2_cr_in1_ok
+    connect \cr_in2_ok \pdecode2_cr_in2_ok
+    connect \cr_in2_ok$1 \pdecode2_cr_in2_ok$1
+    connect \cia$2 \pdecode2_cia
+    connect \lk \pdecode2_lk
+    connect \fast1_ok \pdecode2_fast1_ok
+    connect \fast2_ok \pdecode2_fast2_ok
+    connect \msr$3 \pdecode2_msr
+    connect \traptype \pdecode2_traptype
+    connect \trapaddr \pdecode2_trapaddr
+    connect \spr1_ok \pdecode2_spr1_ok
+    connect \input_cr \pdecode2_input_cr
+    connect \output_cr \pdecode2_output_cr
+    connect \reg3_ok \pdecode2_reg3_ok
+    connect \byte_reverse \pdecode2_byte_reverse
+    connect \sign_extend \pdecode2_sign_extend
+    connect \ldst_mode \pdecode2_ldst_mode
+    connect \reg1 \pdecode2_reg1
+    connect \reg2 \pdecode2_reg2
+    connect \reg3 \pdecode2_reg3
+    connect \cr_in1 \pdecode2_cr_in1
+    connect \cr_in2 \pdecode2_cr_in2
+    connect \cr_in2$4 \pdecode2_cr_in2$2
+    connect \fast1 \pdecode2_fast1
+    connect \fast2 \pdecode2_fast2
+    connect \spr1 \pdecode2_spr1
+    connect \rego \pdecode2_rego
+    connect \ea \pdecode2_ea
+    connect \cr_out \pdecode2_cr_out
+    connect \fasto1 \pdecode2_fasto1
+    connect \fasto2 \pdecode2_fasto2
+    connect \spro \pdecode2_spro
+  end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147104,7 +147459,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 25 \oper_i_alu_alu0__insn_type
+  wire width 7 \fus_oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147118,77 +147473,49 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 26 \oper_i_alu_alu0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 27 \imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 28 \imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 29 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 30 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 31 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 32 \oe_ok
+  wire width 11 \fus_oper_i_alu_alu0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \oper_i_alu_alu0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
-  wire width 1 output 34 \invert_a
+  wire width 64 \fus_oper_i_alu_alu0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \oper_i_alu_alu0__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
-  wire width 1 output 36 \zero_a
+  wire width 1 \fus_oper_i_alu_alu0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 37 \oper_i_alu_alu0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
-  wire width 1 output 38 \invert_out
+  wire width 1 \fus_oper_i_alu_alu0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 39 \oper_i_alu_alu0__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
-  wire width 1 output 40 \write_cr0
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \fus_oper_i_alu_alu0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_alu0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_alu0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 41 \oper_i_alu_alu0__input_carry
+  wire width 1 \fus_oper_i_alu_alu0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_alu0__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
-  wire width 2 output 42 \input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 43 \oper_i_alu_alu0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
-  wire width 1 output 44 \output_carry
+  wire width 2 \fus_oper_i_alu_alu0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 45 \oper_i_alu_alu0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
-  wire width 1 output 46 \is_32bit
+  wire width 1 \fus_oper_i_alu_alu0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 47 \oper_i_alu_alu0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
-  wire width 1 output 48 \is_signed
+  wire width 1 \fus_oper_i_alu_alu0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 49 \oper_i_alu_alu0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
-  wire width 4 output 50 \data_len
+  wire width 1 \fus_oper_i_alu_alu0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 51 \oper_i_alu_alu0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
-  wire width 32 output 52 \insn
+  wire width 4 \fus_oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \fus_oper_i_alu_alu0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 53 \cu_issue_i
+  wire width 1 \fus_cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 54 \cu_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 55 \reg1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 56 \reg2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
-  wire width 1 output 57 \xer_in
+  wire width 1 \fus_cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 \fus_cu_rdmaskn_i
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147263,7 +147590,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 58 \oper_i_alu_cr0__insn_type
+  wire width 7 \fus_oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147277,31 +147604,21 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 59 \oper_i_alu_cr0__fn_unit
+  wire width 11 \fus_oper_i_alu_cr0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 60 \oper_i_alu_cr0__insn
+  wire width 32 \fus_oper_i_alu_cr0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 61 \oper_i_alu_cr0__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
-  wire width 1 output 62 \read_cr_whole
+  wire width 1 \fus_oper_i_alu_cr0__read_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 63 \oper_i_alu_cr0__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
-  wire width 1 output 64 \write_cr_whole
+  wire width 1 \fus_oper_i_alu_cr0__write_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 65 \cu_issue_i$1
+  wire width 1 \fus_cu_issue_i$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 66 \cu_busy_o$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 67 \cr_in1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 68 \cr_in2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 69 \cr_in2_ok$3
+  wire width 1 \fus_cu_busy_o$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 \fus_cu_rdmaskn_i$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 70 \oper_i_alu_branch0__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
-  wire width 64 output 71 \cia$4
+  wire width 64 \fus_oper_i_alu_branch0__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147376,7 +147693,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 72 \oper_i_alu_branch0__insn_type
+  wire width 7 \fus_oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147390,23 +147707,23 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 73 \oper_i_alu_branch0__fn_unit
+  wire width 11 \fus_oper_i_alu_branch0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 74 \oper_i_alu_branch0__insn
+  wire width 32 \fus_oper_i_alu_branch0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 75 \oper_i_alu_branch0__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
-  wire width 1 output 76 \lk
+  wire width 64 \fus_oper_i_alu_branch0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_branch0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_branch0__lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 77 \oper_i_alu_branch0__is_32bit
+  wire width 1 \fus_oper_i_alu_branch0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 78 \cu_issue_i$5
+  wire width 1 \fus_cu_issue_i$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 79 \cu_busy_o$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 80 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 81 \fast2_ok
+  wire width 1 \fus_cu_busy_o$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 \fus_cu_rdmaskn_i$8
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147481,7 +147798,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 82 \oper_i_alu_trap0__insn_type
+  wire width 7 \fus_oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147495,29 +147812,25 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 83 \oper_i_alu_trap0__fn_unit
+  wire width 11 \fus_oper_i_alu_trap0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 84 \oper_i_alu_trap0__insn
+  wire width 32 \fus_oper_i_alu_trap0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 85 \oper_i_alu_trap0__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
-  wire width 64 output 86 \msr$7
+  wire width 64 \fus_oper_i_alu_trap0__msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 87 \oper_i_alu_trap0__cia
+  wire width 64 \fus_oper_i_alu_trap0__cia
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 88 \oper_i_alu_trap0__is_32bit
+  wire width 1 \fus_oper_i_alu_trap0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 5 output 89 \oper_i_alu_trap0__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
-  wire width 5 output 90 \traptype
+  wire width 5 \fus_oper_i_alu_trap0__traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 13 output 91 \oper_i_alu_trap0__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
-  wire width 13 output 92 \trapaddr
+  wire width 13 \fus_oper_i_alu_trap0__trapaddr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 93 \cu_issue_i$8
+  wire width 1 \fus_cu_issue_i$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 94 \cu_busy_o$9
+  wire width 1 \fus_cu_busy_o$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 \fus_cu_rdmaskn_i$11
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147592,7 +147905,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 95 \oper_i_alu_logical0__insn_type
+  wire width 7 \fus_oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147606,241 +147919,49 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 96 \oper_i_alu_logical0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 97 \oper_i_alu_logical0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 98 \oper_i_alu_logical0__zero_a
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 99 \oper_i_alu_logical0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 100 \oper_i_alu_logical0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 101 \oper_i_alu_logical0__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 102 \oper_i_alu_logical0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 103 \oper_i_alu_logical0__is_32bit
+  wire width 11 \fus_oper_i_alu_logical0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 104 \oper_i_alu_logical0__is_signed
+  wire width 64 \fus_oper_i_alu_logical0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 105 \oper_i_alu_logical0__data_len
+  wire width 1 \fus_oper_i_alu_logical0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 106 \oper_i_alu_logical0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 107 \cu_issue_i$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 108 \cu_busy_o$11
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
+  wire width 1 \fus_oper_i_alu_logical0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 109 \oper_i_alu_spr0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
+  wire width 1 \fus_oper_i_alu_logical0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 110 \oper_i_alu_spr0__fn_unit
+  wire width 1 \fus_oper_i_alu_logical0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 111 \oper_i_alu_spr0__insn
+  wire width 1 \fus_oper_i_alu_logical0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 112 \oper_i_alu_spr0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 113 \cu_issue_i$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 114 \cu_busy_o$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 115 \spr1_ok
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
+  wire width 1 \fus_oper_i_alu_logical0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 116 \oper_i_alu_mul0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
+  wire width 1 \fus_oper_i_alu_logical0__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 117 \oper_i_alu_mul0__fn_unit
+  wire width 2 \fus_oper_i_alu_logical0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 118 \oper_i_alu_mul0__invert_a
+  wire width 1 \fus_oper_i_alu_logical0__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 119 \oper_i_alu_mul0__zero_a
+  wire width 1 \fus_oper_i_alu_logical0__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 120 \oper_i_alu_mul0__invert_out
+  wire width 1 \fus_oper_i_alu_logical0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 121 \oper_i_alu_mul0__write_cr0
+  wire width 1 \fus_oper_i_alu_logical0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 122 \oper_i_alu_mul0__is_32bit
+  wire width 1 \fus_oper_i_alu_logical0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 123 \oper_i_alu_mul0__is_signed
+  wire width 4 \fus_oper_i_alu_logical0__data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 124 \oper_i_alu_mul0__insn
+  wire width 32 \fus_oper_i_alu_logical0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 125 \cu_issue_i$14
+  wire width 1 \fus_cu_issue_i$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 126 \cu_busy_o$15
+  wire width 1 \fus_cu_busy_o$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 2 \fus_cu_rdmaskn_i$14
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -147915,7 +148036,7 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 127 \oper_i_alu_shift_rot0__insn_type
+  wire width 7 \fus_oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147929,35 +148050,17 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 128 \oper_i_alu_shift_rot0__fn_unit
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 130 \oper_i_alu_shift_rot0__input_carry
+  wire width 11 \fus_oper_i_alu_spr0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 131 \oper_i_alu_shift_rot0__output_carry
+  wire width 32 \fus_oper_i_alu_spr0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 132 \oper_i_alu_shift_rot0__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
-  wire width 1 output 133 \input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 134 \oper_i_alu_shift_rot0__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
-  wire width 1 output 135 \output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 136 \oper_i_alu_shift_rot0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 137 \oper_i_alu_shift_rot0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 138 \oper_i_alu_shift_rot0__insn
+  wire width 1 \fus_oper_i_alu_spr0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 139 \cu_issue_i$16
+  wire width 1 \fus_cu_issue_i$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 140 \cu_busy_o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 141 \reg3_ok
+  wire width 1 \fus_cu_busy_o$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 \fus_cu_rdmaskn_i$17
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148032,491 +148135,53 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 142 \oper_i_ldst_ldst0__insn_type
+  wire width 7 \fus_oper_i_alu_mul0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 143 \oper_i_ldst_ldst0__zero_a
+  wire width 11 \fus_oper_i_alu_mul0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 144 \oper_i_ldst_ldst0__is_32bit
+  wire width 64 \fus_oper_i_alu_mul0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 145 \oper_i_ldst_ldst0__is_signed
+  wire width 1 \fus_oper_i_alu_mul0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 146 \oper_i_ldst_ldst0__data_len
+  wire width 1 \fus_oper_i_alu_mul0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 147 \oper_i_ldst_ldst0__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
-  wire width 1 output 148 \byte_reverse
+  wire width 1 \fus_oper_i_alu_mul0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 149 \oper_i_ldst_ldst0__sign_extend
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
-  wire width 1 output 150 \sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
+  wire width 1 \fus_oper_i_alu_mul0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 151 \oper_i_ldst_ldst0__ldst_mode
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
-  wire width 2 output 152 \ldst_mode
+  wire width 1 \fus_oper_i_alu_mul0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \fus_oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 153 \cu_issue_i$18
+  wire width 1 \fus_cu_issue_i$18
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 154 \cu_busy_o$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 155 \reg1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 156 \cu_rd__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 157 \cu_rd__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 158 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 159 \cu_rd__rel_o$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 160 \cu_rd__go_i$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 161 \src1_i$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 162 \cu_rd__rel_o$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 163 \cu_rd__go_i$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 164 \src1_i$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 165 \cu_rd__rel_o$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 166 \cu_rd__go_i$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 167 \src1_i$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 168 \cu_rd__rel_o$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 169 \cu_rd__go_i$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 170 \src1_i$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 171 \cu_rd__rel_o$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 172 \cu_rd__go_i$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 173 \src1_i$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 174 \cu_rd__rel_o$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 175 \cu_rd__go_i$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 176 \src1_i$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 177 \cu_rd__rel_o$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 178 \cu_rd__go_i$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 179 \src1_i$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 180 \reg2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 181 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 182 \src2_i$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 183 \src2_i$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 184 \src2_i$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 185 \src2_i$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 186 \src2_i$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 187 \src2_i$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 188 \reg3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 189 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 190 \cr_in1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 191 \cu_rd__rel_o$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 192 \cu_rd__go_i$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 193 \cr_in2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 194 \cr_in2$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 195 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 196 \src1_i$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 197 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 198 \src2_i$51
-  attribute \enum_base_type "SPR"
-  attribute \enum_value_0000000001 "XER"
-  attribute \enum_value_0000000011 "DSCR"
-  attribute \enum_value_0000001000 "LR"
-  attribute \enum_value_0000001001 "CTR"
-  attribute \enum_value_0000001101 "AMR"
-  attribute \enum_value_0000010001 "DSCR_priv"
-  attribute \enum_value_0000010010 "DSISR"
-  attribute \enum_value_0000010011 "DAR"
-  attribute \enum_value_0000010110 "DEC"
-  attribute \enum_value_0000011010 "SRR0"
-  attribute \enum_value_0000011011 "SRR1"
-  attribute \enum_value_0000011100 "CFAR"
-  attribute \enum_value_0000011101 "AMR_priv"
-  attribute \enum_value_0000110000 "PIDR"
-  attribute \enum_value_0000111101 "IAMR"
-  attribute \enum_value_0010000000 "TFHAR"
-  attribute \enum_value_0010000001 "TFIAR"
-  attribute \enum_value_0010000010 "TEXASR"
-  attribute \enum_value_0010000011 "TEXASRU"
-  attribute \enum_value_0010001000 "CTRL"
-  attribute \enum_value_0010010000 "TIDR"
-  attribute \enum_value_0010011000 "CTRL_priv"
-  attribute \enum_value_0010011001 "FSCR"
-  attribute \enum_value_0010011101 "UAMOR"
-  attribute \enum_value_0010011110 "GSR"
-  attribute \enum_value_0010011111 "PSPB"
-  attribute \enum_value_0010110000 "DPDES"
-  attribute \enum_value_0010110100 "DAWR0"
-  attribute \enum_value_0010111010 "RPR"
-  attribute \enum_value_0010111011 "CIABR"
-  attribute \enum_value_0010111100 "DAWRX0"
-  attribute \enum_value_0010111110 "HFSCR"
-  attribute \enum_value_0100000000 "VRSAVE"
-  attribute \enum_value_0100000011 "SPRG3"
-  attribute \enum_value_0100001100 "TB"
-  attribute \enum_value_0100001101 "TBU"
-  attribute \enum_value_0100010000 "SPRG0_priv"
-  attribute \enum_value_0100010001 "SPRG1_priv"
-  attribute \enum_value_0100010010 "SPRG2_priv"
-  attribute \enum_value_0100010011 "SPRG3_priv"
-  attribute \enum_value_0100011011 "CIR"
-  attribute \enum_value_0100011100 "TBL"
-  attribute \enum_value_0100011101 "TBU_hypv"
-  attribute \enum_value_0100011110 "TBU40"
-  attribute \enum_value_0100011111 "PVR"
-  attribute \enum_value_0100110000 "HSPRG0"
-  attribute \enum_value_0100110001 "HSPRG1"
-  attribute \enum_value_0100110010 "HDSISR"
-  attribute \enum_value_0100110011 "HDAR"
-  attribute \enum_value_0100110100 "SPURR"
-  attribute \enum_value_0100110101 "PURR"
-  attribute \enum_value_0100110110 "HDEC"
-  attribute \enum_value_0100111001 "HRMOR"
-  attribute \enum_value_0100111010 "HSRR0"
-  attribute \enum_value_0100111011 "HSRR1"
-  attribute \enum_value_0100111110 "LPCR"
-  attribute \enum_value_0100111111 "LPIDR"
-  attribute \enum_value_0101010000 "HMER"
-  attribute \enum_value_0101010001 "HMEER"
-  attribute \enum_value_0101010010 "PCR"
-  attribute \enum_value_0101010011 "HEIR"
-  attribute \enum_value_0101011101 "AMOR"
-  attribute \enum_value_0110111110 "TIR"
-  attribute \enum_value_0111010000 "PTCR"
-  attribute \enum_value_1100000000 "SIER"
-  attribute \enum_value_1100000001 "MMCR2"
-  attribute \enum_value_1100000010 "MMCRA"
-  attribute \enum_value_1100000011 "PMC1"
-  attribute \enum_value_1100000100 "PMC2"
-  attribute \enum_value_1100000101 "PMC3"
-  attribute \enum_value_1100000110 "PMC4"
-  attribute \enum_value_1100000111 "PMC5"
-  attribute \enum_value_1100001000 "PMC6"
-  attribute \enum_value_1100001011 "MMCR0"
-  attribute \enum_value_1100001100 "SIAR"
-  attribute \enum_value_1100001101 "SDAR"
-  attribute \enum_value_1100001110 "MMCR1"
-  attribute \enum_value_1100010000 "SIER_priv"
-  attribute \enum_value_1100010001 "MMCR2_priv"
-  attribute \enum_value_1100010010 "MMCRA_priv"
-  attribute \enum_value_1100010011 "PMC1_priv"
-  attribute \enum_value_1100010100 "PMC2_priv"
-  attribute \enum_value_1100010101 "PMC3_priv"
-  attribute \enum_value_1100010110 "PMC4_priv"
-  attribute \enum_value_1100010111 "PMC5_priv"
-  attribute \enum_value_1100011000 "PMC6_priv"
-  attribute \enum_value_1100011011 "MMCR0_priv"
-  attribute \enum_value_1100011100 "SIAR_priv"
-  attribute \enum_value_1100011101 "SDAR_priv"
-  attribute \enum_value_1100011110 "MMCR1_priv"
-  attribute \enum_value_1100100000 "BESCRS"
-  attribute \enum_value_1100100001 "BESCRSU"
-  attribute \enum_value_1100100010 "BESCRR"
-  attribute \enum_value_1100100011 "BESCRRU"
-  attribute \enum_value_1100100100 "EBBHR"
-  attribute \enum_value_1100100101 "EBBRR"
-  attribute \enum_value_1100100110 "BESCR"
-  attribute \enum_value_1100101000 "reserved808"
-  attribute \enum_value_1100101001 "reserved809"
-  attribute \enum_value_1100101010 "reserved810"
-  attribute \enum_value_1100101011 "reserved811"
-  attribute \enum_value_1100101111 "TAR"
-  attribute \enum_value_1100110000 "ASDR"
-  attribute \enum_value_1100110111 "PSSCR"
-  attribute \enum_value_1101010000 "IC"
-  attribute \enum_value_1101010001 "VTB"
-  attribute \enum_value_1101010111 "PSSCR_hypv"
-  attribute \enum_value_1110000000 "PPR"
-  attribute \enum_value_1110000010 "PPR32"
-  attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 10 output 199 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 200 \src2_i$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 201 \rego
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 202 \cu_wr__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 203 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 204 \cu_wr__rel_o$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 205 \cu_wr__go_i$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 206 \cu_wr__rel_o$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 207 \cu_wr__go_i$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 208 \cu_wr__rel_o$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 209 \cu_wr__go_i$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 210 \cu_wr__rel_o$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 211 \cu_wr__go_i$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 212 \cu_wr__rel_o$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 213 \cu_wr__go_i$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 214 \cu_wr__rel_o$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 215 \cu_wr__go_i$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 216 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 217 \cu_wr__rel_o$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 218 \cu_wr__go_i$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 219 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 220 \dest1_o$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 221 \dest1_o$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 222 \dest1_o$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 223 \dest1_o$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 224 \dest1_o$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 225 \dest1_o$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 226 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 227 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 228 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 229 \ea$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 230 \cr_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 231 \fasto1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 232 \cu_wr__rel_o$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 233 \cu_wr__go_i$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 234 \dest1_o$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 235 \fasto2
-  attribute \enum_base_type "SPR"
-  attribute \enum_value_0000000001 "XER"
-  attribute \enum_value_0000000011 "DSCR"
-  attribute \enum_value_0000001000 "LR"
-  attribute \enum_value_0000001001 "CTR"
-  attribute \enum_value_0000001101 "AMR"
-  attribute \enum_value_0000010001 "DSCR_priv"
-  attribute \enum_value_0000010010 "DSISR"
-  attribute \enum_value_0000010011 "DAR"
-  attribute \enum_value_0000010110 "DEC"
-  attribute \enum_value_0000011010 "SRR0"
-  attribute \enum_value_0000011011 "SRR1"
-  attribute \enum_value_0000011100 "CFAR"
-  attribute \enum_value_0000011101 "AMR_priv"
-  attribute \enum_value_0000110000 "PIDR"
-  attribute \enum_value_0000111101 "IAMR"
-  attribute \enum_value_0010000000 "TFHAR"
-  attribute \enum_value_0010000001 "TFIAR"
-  attribute \enum_value_0010000010 "TEXASR"
-  attribute \enum_value_0010000011 "TEXASRU"
-  attribute \enum_value_0010001000 "CTRL"
-  attribute \enum_value_0010010000 "TIDR"
-  attribute \enum_value_0010011000 "CTRL_priv"
-  attribute \enum_value_0010011001 "FSCR"
-  attribute \enum_value_0010011101 "UAMOR"
-  attribute \enum_value_0010011110 "GSR"
-  attribute \enum_value_0010011111 "PSPB"
-  attribute \enum_value_0010110000 "DPDES"
-  attribute \enum_value_0010110100 "DAWR0"
-  attribute \enum_value_0010111010 "RPR"
-  attribute \enum_value_0010111011 "CIABR"
-  attribute \enum_value_0010111100 "DAWRX0"
-  attribute \enum_value_0010111110 "HFSCR"
-  attribute \enum_value_0100000000 "VRSAVE"
-  attribute \enum_value_0100000011 "SPRG3"
-  attribute \enum_value_0100001100 "TB"
-  attribute \enum_value_0100001101 "TBU"
-  attribute \enum_value_0100010000 "SPRG0_priv"
-  attribute \enum_value_0100010001 "SPRG1_priv"
-  attribute \enum_value_0100010010 "SPRG2_priv"
-  attribute \enum_value_0100010011 "SPRG3_priv"
-  attribute \enum_value_0100011011 "CIR"
-  attribute \enum_value_0100011100 "TBL"
-  attribute \enum_value_0100011101 "TBU_hypv"
-  attribute \enum_value_0100011110 "TBU40"
-  attribute \enum_value_0100011111 "PVR"
-  attribute \enum_value_0100110000 "HSPRG0"
-  attribute \enum_value_0100110001 "HSPRG1"
-  attribute \enum_value_0100110010 "HDSISR"
-  attribute \enum_value_0100110011 "HDAR"
-  attribute \enum_value_0100110100 "SPURR"
-  attribute \enum_value_0100110101 "PURR"
-  attribute \enum_value_0100110110 "HDEC"
-  attribute \enum_value_0100111001 "HRMOR"
-  attribute \enum_value_0100111010 "HSRR0"
-  attribute \enum_value_0100111011 "HSRR1"
-  attribute \enum_value_0100111110 "LPCR"
-  attribute \enum_value_0100111111 "LPIDR"
-  attribute \enum_value_0101010000 "HMER"
-  attribute \enum_value_0101010001 "HMEER"
-  attribute \enum_value_0101010010 "PCR"
-  attribute \enum_value_0101010011 "HEIR"
-  attribute \enum_value_0101011101 "AMOR"
-  attribute \enum_value_0110111110 "TIR"
-  attribute \enum_value_0111010000 "PTCR"
-  attribute \enum_value_1100000000 "SIER"
-  attribute \enum_value_1100000001 "MMCR2"
-  attribute \enum_value_1100000010 "MMCRA"
-  attribute \enum_value_1100000011 "PMC1"
-  attribute \enum_value_1100000100 "PMC2"
-  attribute \enum_value_1100000101 "PMC3"
-  attribute \enum_value_1100000110 "PMC4"
-  attribute \enum_value_1100000111 "PMC5"
-  attribute \enum_value_1100001000 "PMC6"
-  attribute \enum_value_1100001011 "MMCR0"
-  attribute \enum_value_1100001100 "SIAR"
-  attribute \enum_value_1100001101 "SDAR"
-  attribute \enum_value_1100001110 "MMCR1"
-  attribute \enum_value_1100010000 "SIER_priv"
-  attribute \enum_value_1100010001 "MMCR2_priv"
-  attribute \enum_value_1100010010 "MMCRA_priv"
-  attribute \enum_value_1100010011 "PMC1_priv"
-  attribute \enum_value_1100010100 "PMC2_priv"
-  attribute \enum_value_1100010101 "PMC3_priv"
-  attribute \enum_value_1100010110 "PMC4_priv"
-  attribute \enum_value_1100010111 "PMC5_priv"
-  attribute \enum_value_1100011000 "PMC6_priv"
-  attribute \enum_value_1100011011 "MMCR0_priv"
-  attribute \enum_value_1100011100 "SIAR_priv"
-  attribute \enum_value_1100011101 "SDAR_priv"
-  attribute \enum_value_1100011110 "MMCR1_priv"
-  attribute \enum_value_1100100000 "BESCRS"
-  attribute \enum_value_1100100001 "BESCRSU"
-  attribute \enum_value_1100100010 "BESCRR"
-  attribute \enum_value_1100100011 "BESCRRU"
-  attribute \enum_value_1100100100 "EBBHR"
-  attribute \enum_value_1100100101 "EBBRR"
-  attribute \enum_value_1100100110 "BESCR"
-  attribute \enum_value_1100101000 "reserved808"
-  attribute \enum_value_1100101001 "reserved809"
-  attribute \enum_value_1100101010 "reserved810"
-  attribute \enum_value_1100101011 "reserved811"
-  attribute \enum_value_1100101111 "TAR"
-  attribute \enum_value_1100110000 "ASDR"
-  attribute \enum_value_1100110111 "PSSCR"
-  attribute \enum_value_1101010000 "IC"
-  attribute \enum_value_1101010001 "VTB"
-  attribute \enum_value_1101010111 "PSSCR_hypv"
-  attribute \enum_value_1110000000 "PPR"
-  attribute \enum_value_1110000010 "PPR32"
-  attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 10 output 236 \spro
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
-  wire width 32 output 237 \opcode_in
-  attribute \enum_base_type "In1Sel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "RA"
-  attribute \enum_value_010 "RA_OR_ZERO"
-  attribute \enum_value_011 "SPR"
-  attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
-  wire width 3 output 238 \in1_sel
-  attribute \enum_base_type "In2Sel"
-  attribute \enum_value_0000 "NONE"
-  attribute \enum_value_0001 "RB"
-  attribute \enum_value_0010 "CONST_UI"
-  attribute \enum_value_0011 "CONST_SI"
-  attribute \enum_value_0100 "CONST_UI_HI"
-  attribute \enum_value_0101 "CONST_SI_HI"
-  attribute \enum_value_0110 "CONST_LI"
-  attribute \enum_value_0111 "CONST_BD"
-  attribute \enum_value_1000 "CONST_DS"
-  attribute \enum_value_1001 "CONST_M1"
-  attribute \enum_value_1010 "CONST_SH"
-  attribute \enum_value_1011 "CONST_SH32"
-  attribute \enum_value_1100 "SPR"
-  attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
-  wire width 4 output 239 \in2_sel
-  attribute \enum_base_type "In3Sel"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "RS"
-  attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
-  wire width 2 output 240 \in3_sel
-  attribute \enum_base_type "OutSel"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "RT"
-  attribute \enum_value_10 "RA"
-  attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
-  wire width 2 output 241 \out_sel
-  attribute \enum_base_type "RC"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
-  wire width 2 output 242 \rc_sel
-  attribute \enum_base_type "CRInSel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "CR0"
-  attribute \enum_value_010 "BI"
-  attribute \enum_value_011 "BFA"
-  attribute \enum_value_100 "BA_BB"
-  attribute \enum_value_101 "BC"
-  attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
-  wire width 3 output 243 \cr_in
-  attribute \enum_base_type "CROutSel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "CR0"
-  attribute \enum_value_010 "BF"
-  attribute \enum_value_011 "BT"
-  attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
-  wire width 3 output 244 \cr_out$77
+  wire width 1 \fus_cu_busy_o$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 \fus_cu_rdmaskn_i$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148590,8 +148255,8 @@ module \core
   attribute \enum_value_1001000 "OP_MTMSRD"
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
-  wire width 7 output 245 \internal_op
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \fus_oper_i_alu_shift_rot0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -148604,446 +148269,326 @@ module \core
   attribute \enum_value_00100000000 "MUL"
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
-  wire width 11 output 246 \function_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 247 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 248 \ea_ok$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 249 \spro_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 250 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 251 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 252 \cr_out_ok
-  attribute \enum_base_type "LdstLen"
-  attribute \enum_value_0000 "NONE"
-  attribute \enum_value_0001 "is1B"
-  attribute \enum_value_0010 "is2B"
-  attribute \enum_value_0100 "is4B"
-  attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
-  wire width 4 output 253 \ldst_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 254 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 255 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 256 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 257 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 258 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 259 \lk$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 260 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 261 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
-  wire width 1 output 262 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
-  wire width 8 output 263 \asmcode
-  attribute \enum_base_type "Form"
-  attribute \enum_value_00000 "NONE"
-  attribute \enum_value_00001 "I"
-  attribute \enum_value_00010 "B"
-  attribute \enum_value_00011 "SC"
-  attribute \enum_value_00100 "D"
-  attribute \enum_value_00101 "DS"
-  attribute \enum_value_00110 "DQ"
-  attribute \enum_value_00111 "DX"
-  attribute \enum_value_01000 "X"
-  attribute \enum_value_01001 "XL"
-  attribute \enum_value_01010 "XFX"
-  attribute \enum_value_01011 "XFL"
-  attribute \enum_value_01100 "XX1"
-  attribute \enum_value_01101 "XX2"
-  attribute \enum_value_01110 "XX3"
-  attribute \enum_value_01111 "XX4"
-  attribute \enum_value_10000 "XS"
-  attribute \enum_value_10001 "XO"
-  attribute \enum_value_10010 "A"
-  attribute \enum_value_10011 "M"
-  attribute \enum_value_10100 "MD"
-  attribute \enum_value_10101 "MDS"
-  attribute \enum_value_10110 "VA"
-  attribute \enum_value_10111 "VC"
-  attribute \enum_value_11000 "VX"
-  attribute \enum_value_11001 "EVX"
-  attribute \enum_value_11010 "EVS"
-  attribute \enum_value_11011 "Z22"
-  attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
-  wire width 5 output 264 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 265 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 266 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
-  wire width 8 output 267 \asmcode$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 268 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 269 \cu_shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 270 \cu_go_die_i$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 271 \cu_shadown_i$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 272 \cu_go_die_i$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 273 \cu_shadown_i$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 274 \cu_go_die_i$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 275 \cu_shadown_i$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 276 \cu_go_die_i$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 277 \cu_shadown_i$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 278 \cu_go_die_i$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 279 \cu_shadown_i$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 280 \cu_go_die_i$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 281 \cu_shadown_i$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 282 \cu_go_die_i$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 283 \cu_shadown_i$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 284 \cu_go_die_i$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
-  wire width 1 output 285 \load_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
-  wire width 1 output 286 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 287 \cu_shadown_i$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 288 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 289 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 290 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 291 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 292 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 output 293 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 294 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 295 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 296 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 297 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 298 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 299 \ldst_port0_is_ld_i$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 300 \ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 301 \ldst_port0_is_st_i$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 302 \ldst_port0_data_len$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 output 303 \ldst_port0_addr_i$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 304 \ldst_port0_addr_i_ok$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 305 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 306 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 307 \ldst_port0_addr_ok_o$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 308 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 309 \ldst_port0_ld_data_o$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 310 \ldst_port0_ld_data_o_ok$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 311 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 312 \ldst_port0_st_data_i_ok$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 313 \ldst_port0_st_data_i$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 314 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 315 \ldst_port0_addr_exc_o$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 316 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 317 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 318 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 319 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 output 320 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 321 \ldst_port0_go_die_i$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 322 \ldst_port0_busy_o$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 323 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 324 \x_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 325 \dbus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 326 \dbus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 327 \dbus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 328 \dbus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 329 \dbus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 330 \dbus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 331 \dbus__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 332 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 333 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 334 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 335 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 336 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 337 \m_busy_o
-  cell \pdecode2 \pdecode2
-    connect \bigendian \bigendian
-    connect \raw_opcode_in \raw_opcode_in
-    connect \msr \msr
-    connect \cia \cia
-    connect \insn_type \insn_type
-    connect \fn_unit \fn_unit
-    connect \imm \imm
-    connect \imm_ok \imm_ok
-    connect \rc \rc
-    connect \rc_ok \rc_ok
-    connect \oe \oe
-    connect \oe_ok \oe_ok
-    connect \invert_a \invert_a
-    connect \zero_a \zero_a
-    connect \invert_out \invert_out
-    connect \write_cr0 \write_cr0
-    connect \input_carry \input_carry
-    connect \output_carry \output_carry
-    connect \is_32bit \is_32bit
-    connect \is_signed \is_signed
-    connect \data_len \data_len
-    connect \insn \insn
-    connect \reg1_ok \reg1_ok
-    connect \reg2_ok \reg2_ok
-    connect \xer_in \xer_in
-    connect \read_cr_whole \read_cr_whole
-    connect \write_cr_whole \write_cr_whole
-    connect \cr_in1_ok \cr_in1_ok
-    connect \cr_in2_ok \cr_in2_ok
-    connect \cr_in2_ok$1 \cr_in2_ok$3
-    connect \cia$2 \cia$4
-    connect \lk \lk
-    connect \fast1_ok \fast1_ok
-    connect \fast2_ok \fast2_ok
-    connect \msr$3 \msr$7
-    connect \traptype \traptype
-    connect \trapaddr \trapaddr
-    connect \spr1_ok \spr1_ok
-    connect \input_cr \input_cr
-    connect \output_cr \output_cr
-    connect \reg3_ok \reg3_ok
-    connect \byte_reverse \byte_reverse
-    connect \sign_extend \sign_extend
-    connect \ldst_mode \ldst_mode
-    connect \reg1 \reg1
-    connect \reg2 \reg2
-    connect \reg3 \reg3
-    connect \cr_in1 \cr_in1
-    connect \cr_in2 \cr_in2
-    connect \cr_in2$4 \cr_in2$49
-    connect \fast1 \fast1
-    connect \fast2 \fast2
-    connect \spr1 \spr1
-    connect \rego \rego
-    connect \ea \ea
-    connect \cr_out \cr_out
-    connect \fasto1 \fasto1
-    connect \fasto2 \fasto2
-    connect \spro \spro
-    connect \opcode_in \opcode_in
-    connect \in1_sel \in1_sel
-    connect \in2_sel \in2_sel
-    connect \in3_sel \in3_sel
-    connect \out_sel \out_sel
-    connect \rc_sel \rc_sel
-    connect \cr_in \cr_in
-    connect \cr_out$5 \cr_out$77
-    connect \internal_op \internal_op
-    connect \function_unit \function_unit
-    connect \rego_ok \rego_ok
-    connect \ea_ok \ea_ok$78
-    connect \spro_ok \spro_ok
-    connect \fasto1_ok \fasto1_ok
-    connect \fasto2_ok \fasto2_ok
-    connect \cr_out_ok \cr_out_ok
-    connect \ldst_len \ldst_len
-    connect \inv_a \inv_a
-    connect \inv_out \inv_out
-    connect \cry_out \cry_out
-    connect \is_32b \is_32b
-    connect \sgn \sgn
-    connect \lk$6 \lk$79
-    connect \br \br
-    connect \sgn_ext \sgn_ext
-    connect \xer_out \xer_out
-    connect \asmcode \asmcode
-    connect \form \form
-    connect \rsrv \rsrv
-    connect \sgl_pipe \sgl_pipe
-    connect \asmcode$7 \asmcode$80
-  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \fus_oper_i_alu_alu0__imm_data__imm
+  wire width 11 \fus_oper_i_alu_shift_rot0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_alu0__imm_data__imm_ok
+  wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_alu0__rc__rc
+  wire width 1 \fus_oper_i_alu_shift_rot0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_alu0__rc__rc_ok
+  wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_alu0__oe__oe
+  wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_alu0__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 \fus_cu_rdmaskn_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 \fus_cu_rdmaskn_i$110
+  wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \fus_oper_i_alu_branch0__imm_data__imm
+  wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_branch0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 \fus_cu_rdmaskn_i$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 \fus_cu_rdmaskn_i$112
+  wire width 2 \fus_oper_i_alu_shift_rot0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \fus_oper_i_alu_logical0__imm_data__imm
+  wire width 1 \fus_oper_i_alu_shift_rot0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_logical0__imm_data__imm_ok
+  wire width 1 \fus_oper_i_alu_shift_rot0__input_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_logical0__rc__rc
+  wire width 1 \fus_oper_i_alu_shift_rot0__output_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_logical0__rc__rc_ok
+  wire width 1 \fus_oper_i_alu_shift_rot0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_logical0__oe__oe
+  wire width 1 \fus_oper_i_alu_shift_rot0__is_signed
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$134
+  wire width 64 \fus_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$135
+  wire width 64 \fus_ea
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_full_cr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
@@ -149051,443 +148596,436 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$136
+  wire width 1 \fus_cr_a_ok$98
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$137
+  wire width 1 \fus_cr_a_ok$99
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$138
+  wire width 1 \fus_cr_a_ok$100
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$139
+  wire width 1 \fus_cr_a_ok$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$140
+  wire width 4 \fus_dest2_o$102
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 \fus_dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$141
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$142
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$143
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ca_ok$145
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ca_ok$146
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$147
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$148
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$149
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ov_ok$150
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ov_ok$151
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 \fus_dest4_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 \fus_dest5_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$152
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_so_ok$153
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_so_ok$154
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest5_o$155
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest4_o$156
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest4_o$157
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast1_ok$158
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast1_ok$159
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$160
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$161
+  wire width 64 \fus_dest2_o$125
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest3_o$126
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast2_ok$162
+  wire width 1 \fus_fast2_ok$127
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$163
+  wire width 64 \fus_dest2_o$128
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$164
+  wire width 64 \fus_dest3_o$129
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_nia_ok$165
+  wire width 1 \fus_nia_ok$130
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$166
+  wire width 64 \fus_dest3_o$131
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest4_o$167
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   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_msr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest5_o$168
+  wire width 64 \fus_dest5_o$133
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$169
+  wire width 64 \fus_dest2_o$134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 \fus_ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 \fus_ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 \fus_ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 \fus_ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 \fus_ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 \fus_ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \fus_ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \fus_ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_ldst_port0_st_data_i_ok
   cell \fus \fus
-    connect \ad__go_i \ad__go_i
-    connect \ad__rel_o \ad__rel_o
-    connect \st__go_i \st__go_i
-    connect \st__rel_o \st__rel_o
+    connect \cu_ad__go_i \cu_ad__go_i
+    connect \cu_ad__rel_o \cu_ad__rel_o
+    connect \cu_st__go_i \cu_st__go_i
+    connect \cu_st__rel_o \cu_st__rel_o
     connect \rst \rst
     connect \clk \clk
-    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
-    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
+    connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type
+    connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit
     connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm
     connect \oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm_ok
     connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc
     connect \oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc_ok
     connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe
     connect \oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe_ok
-    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
-    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
-    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
-    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
-    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
-    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
-    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
-    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
-    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
-    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
-    connect \cu_issue_i \cu_issue_i
-    connect \cu_busy_o \cu_busy_o
+    connect \oper_i_alu_alu0__invert_a \fus_oper_i_alu_alu0__invert_a
+    connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a
+    connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out
+    connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0
+    connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry
+    connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry
+    connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit
+    connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed
+    connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len
+    connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn
+    connect \cu_issue_i \fus_cu_issue_i
+    connect \cu_busy_o \fus_cu_busy_o
     connect \cu_rdmaskn_i \fus_cu_rdmaskn_i
-    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
-    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
-    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
-    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
-    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
-    connect \cu_issue_i$1 \cu_issue_i$1
-    connect \cu_busy_o$2 \cu_busy_o$2
-    connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$110
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-    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
-    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
-    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
+    connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type
+    connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit
+    connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn
+    connect \oper_i_alu_cr0__read_cr_whole \fus_oper_i_alu_cr0__read_cr_whole
+    connect \oper_i_alu_cr0__write_cr_whole \fus_oper_i_alu_cr0__write_cr_whole
+    connect \cu_issue_i$1 \fus_cu_issue_i$3
+    connect \cu_busy_o$2 \fus_cu_busy_o$4
+    connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$5
+    connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia
+    connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type
+    connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit
+    connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn
     connect \oper_i_alu_branch0__imm_data__imm \fus_oper_i_alu_branch0__imm_data__imm
     connect \oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm_ok
-    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
-    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
-    connect \cu_issue_i$4 \cu_issue_i$5
-    connect \cu_busy_o$5 \cu_busy_o$6
-    connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$111
-    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
-    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
-    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
-    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
-    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
-    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
-    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
-    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
-    connect \cu_issue_i$7 \cu_issue_i$8
-    connect \cu_busy_o$8 \cu_busy_o$9
-    connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$112
-    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
-    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
+    connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk
+    connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit
+    connect \cu_issue_i$4 \fus_cu_issue_i$6
+    connect \cu_busy_o$5 \fus_cu_busy_o$7
+    connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$8
+    connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type
+    connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit
+    connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn
+    connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr
+    connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia
+    connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit
+    connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype
+    connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr
+    connect \cu_issue_i$7 \fus_cu_issue_i$9
+    connect \cu_busy_o$8 \fus_cu_busy_o$10
+    connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$11
+    connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type
+    connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit
     connect \oper_i_alu_logical0__imm_data__imm \fus_oper_i_alu_logical0__imm_data__imm
     connect \oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm_ok
     connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc
     connect \oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc_ok
     connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe
     connect \oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe_ok
-    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
-    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
-    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
-    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
-    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
-    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
-    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
-    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
-    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
-    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
-    connect \cu_issue_i$10 \cu_issue_i$10
-    connect \cu_busy_o$11 \cu_busy_o$11
-    connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$113
-    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
-    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
-    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
-    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
-    connect \cu_issue_i$13 \cu_issue_i$12
-    connect \cu_busy_o$14 \cu_busy_o$13
-    connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$114
-    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
-    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
+    connect \oper_i_alu_logical0__invert_a \fus_oper_i_alu_logical0__invert_a
+    connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a
+    connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry
+    connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out
+    connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0
+    connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry
+    connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit
+    connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed
+    connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len
+    connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn
+    connect \cu_issue_i$10 \fus_cu_issue_i$12
+    connect \cu_busy_o$11 \fus_cu_busy_o$13
+    connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$14
+    connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type
+    connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit
+    connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn
+    connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit
+    connect \cu_issue_i$13 \fus_cu_issue_i$15
+    connect \cu_busy_o$14 \fus_cu_busy_o$16
+    connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$17
+    connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type
+    connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit
     connect \oper_i_alu_mul0__imm_data__imm \fus_oper_i_alu_mul0__imm_data__imm
     connect \oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm_ok
     connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc
     connect \oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc_ok
     connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe
     connect \oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe_ok
-    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
-    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
-    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
-    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
-    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
-    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
-    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
-    connect \cu_issue_i$16 \cu_issue_i$14
-    connect \cu_busy_o$17 \cu_busy_o$15
-    connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$115
-    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
-    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
+    connect \oper_i_alu_mul0__invert_a \fus_oper_i_alu_mul0__invert_a
+    connect \oper_i_alu_mul0__zero_a \fus_oper_i_alu_mul0__zero_a
+    connect \oper_i_alu_mul0__invert_out \fus_oper_i_alu_mul0__invert_out
+    connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0
+    connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit
+    connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed
+    connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn
+    connect \cu_issue_i$16 \fus_cu_issue_i$18
+    connect \cu_busy_o$17 \fus_cu_busy_o$19
+    connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$20
+    connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type
+    connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit
     connect \oper_i_alu_shift_rot0__imm_data__imm \fus_oper_i_alu_shift_rot0__imm_data__imm
     connect \oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm_ok
     connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc
     connect \oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc_ok
     connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe
     connect \oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe_ok
-    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
-    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
-    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
-    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
-    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
-    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
-    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
-    connect \cu_issue_i$19 \cu_issue_i$16
-    connect \cu_busy_o$20 \cu_busy_o$17
-    connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$116
-    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
+    connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry
+    connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry
+    connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr
+    connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr
+    connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit
+    connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed
+    connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn
+    connect \cu_issue_i$19 \fus_cu_issue_i$21
+    connect \cu_busy_o$20 \fus_cu_busy_o$22
+    connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$23
+    connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type
     connect \oper_i_ldst_ldst0__imm_data__imm \fus_oper_i_ldst_ldst0__imm_data__imm
     connect \oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm_ok
-    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
+    connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a
     connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc
     connect \oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc_ok
     connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe
     connect \oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe_ok
-    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
-    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
-    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
-    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
-    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
-    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
-    connect \cu_issue_i$22 \cu_issue_i$18
-    connect \cu_busy_o$23 \cu_busy_o$19
-    connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$117
-    connect \cu_rd__rel_o \cu_rd__rel_o
-    connect \cu_rd__go_i \cu_rd__go_i
-    connect \src1_i \src1_i
-    connect \cu_rd__rel_o$25 \cu_rd__rel_o$20
-    connect \cu_rd__go_i$26 \cu_rd__go_i$21
-    connect \src1_i$27 \src1_i$22
-    connect \cu_rd__rel_o$28 \cu_rd__rel_o$23
-    connect \cu_rd__go_i$29 \cu_rd__go_i$24
-    connect \src1_i$30 \src1_i$25
-    connect \cu_rd__rel_o$31 \cu_rd__rel_o$26
-    connect \cu_rd__go_i$32 \cu_rd__go_i$27
-    connect \src1_i$33 \src1_i$28
-    connect \cu_rd__rel_o$34 \cu_rd__rel_o$29
-    connect \cu_rd__go_i$35 \cu_rd__go_i$30
-    connect \src1_i$36 \src1_i$31
-    connect \cu_rd__rel_o$37 \cu_rd__rel_o$32
-    connect \cu_rd__go_i$38 \cu_rd__go_i$33
-    connect \src1_i$39 \src1_i$34
-    connect \cu_rd__rel_o$40 \cu_rd__rel_o$35
-    connect \cu_rd__go_i$41 \cu_rd__go_i$36
-    connect \src1_i$42 \src1_i$37
-    connect \cu_rd__rel_o$43 \cu_rd__rel_o$38
-    connect \cu_rd__go_i$44 \cu_rd__go_i$39
-    connect \src1_i$45 \src1_i$40
-    connect \src2_i \src2_i
-    connect \src2_i$46 \src2_i$41
-    connect \src2_i$47 \src2_i$42
-    connect \src2_i$48 \src2_i$43
-    connect \src2_i$49 \src2_i$44
-    connect \src2_i$50 \src2_i$45
-    connect \src2_i$51 \src2_i$46
+    connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit
+    connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed
+    connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len
+    connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse
+    connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend
+    connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode
+    connect \cu_issue_i$22 \fus_cu_issue_i$24
+    connect \cu_busy_o$23 \fus_cu_busy_o$25
+    connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$26
+    connect \cu_rd__rel_o \fus_cu_rd__rel_o
+    connect \cu_rd__go_i \fus_cu_rd__go_i
+    connect \src1_i \fus_src1_i
+    connect \cu_rd__rel_o$25 \fus_cu_rd__rel_o$27
+    connect \cu_rd__go_i$26 \fus_cu_rd__go_i$28
+    connect \src1_i$27 \fus_src1_i$29
+    connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$30
+    connect \cu_rd__go_i$29 \fus_cu_rd__go_i$31
+    connect \src1_i$30 \fus_src1_i$32
+    connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$33
+    connect \cu_rd__go_i$32 \fus_cu_rd__go_i$34
+    connect \src1_i$33 \fus_src1_i$35
+    connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$36
+    connect \cu_rd__go_i$35 \fus_cu_rd__go_i$37
+    connect \src1_i$36 \fus_src1_i$38
+    connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$39
+    connect \cu_rd__go_i$38 \fus_cu_rd__go_i$40
+    connect \src1_i$39 \fus_src1_i$41
+    connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$42
+    connect \cu_rd__go_i$41 \fus_cu_rd__go_i$43
+    connect \src1_i$42 \fus_src1_i$44
+    connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$45
+    connect \cu_rd__go_i$44 \fus_cu_rd__go_i$46
+    connect \src1_i$45 \fus_src1_i$47
+    connect \src2_i \fus_src2_i
+    connect \src2_i$46 \fus_src2_i$48
+    connect \src2_i$47 \fus_src2_i$49
+    connect \src2_i$48 \fus_src2_i$50
+    connect \src2_i$49 \fus_src2_i$51
+    connect \src2_i$50 \fus_src2_i$52
+    connect \src2_i$51 \fus_src2_i$53
     connect \src3_i \fus_src3_i
-    connect \src3_i$52 \src3_i
-    connect \src3_i$53 \fus_src3_i$118
+    connect \src3_i$52 \fus_src3_i$54
+    connect \src3_i$53 \fus_src3_i$55
     connect \src4_i \fus_src4_i
-    connect \src3_i$54 \fus_src3_i$119
-    connect \src4_i$55 \fus_src4_i$120
+    connect \src3_i$54 \fus_src3_i$56
+    connect \src4_i$55 \fus_src4_i$57
     connect \src6_i \fus_src6_i
-    connect \src4_i$56 \fus_src4_i$121
+    connect \src4_i$56 \fus_src4_i$58
     connect \src5_i \fus_src5_i
-    connect \src3_i$57 \fus_src3_i$122
-    connect \src4_i$58 \fus_src4_i$123
-    connect \cu_rd__rel_o$59 \cu_rd__rel_o$47
-    connect \cu_rd__go_i$60 \cu_rd__go_i$48
-    connect \src3_i$61 \fus_src3_i$124
-    connect \src5_i$62 \fus_src5_i$125
-    connect \src6_i$63 \fus_src6_i$126
-    connect \src1_i$64 \src1_i$50
-    connect \src3_i$65 \fus_src3_i$127
-    connect \src3_i$66 \fus_src3_i$128
-    connect \src2_i$67 \src2_i$51
-    connect \src4_i$68 \fus_src4_i$129
-    connect \src2_i$69 \src2_i$52
+    connect \src3_i$57 \fus_src3_i$59
+    connect \src4_i$58 \fus_src4_i$60
+    connect \cu_rd__rel_o$59 \fus_cu_rd__rel_o$61
+    connect \cu_rd__go_i$60 \fus_cu_rd__go_i$62
+    connect \src3_i$61 \fus_src3_i$63
+    connect \src5_i$62 \fus_src5_i$64
+    connect \src6_i$63 \fus_src6_i$65
+    connect \src1_i$64 \fus_src1_i$66
+    connect \src3_i$65 \fus_src3_i$67
+    connect \src3_i$66 \fus_src3_i$68
+    connect \src2_i$67 \fus_src2_i$69
+    connect \src4_i$68 \fus_src4_i$70
+    connect \src2_i$69 \fus_src2_i$71
     connect \o_ok \fus_o_ok
-    connect \cu_wr__rel_o \cu_wr__rel_o
-    connect \cu_wr__go_i \cu_wr__go_i
-    connect \o_ok$70 \fus_o_ok$130
-    connect \cu_wr__rel_o$71 \cu_wr__rel_o$53
-    connect \cu_wr__go_i$72 \cu_wr__go_i$54
-    connect \o_ok$73 \fus_o_ok$131
-    connect \cu_wr__rel_o$74 \cu_wr__rel_o$55
-    connect \cu_wr__go_i$75 \cu_wr__go_i$56
-    connect \o_ok$76 \fus_o_ok$132
-    connect \cu_wr__rel_o$77 \cu_wr__rel_o$57
-    connect \cu_wr__go_i$78 \cu_wr__go_i$58
-    connect \o_ok$79 \fus_o_ok$133
-    connect \cu_wr__rel_o$80 \cu_wr__rel_o$59
-    connect \cu_wr__go_i$81 \cu_wr__go_i$60
-    connect \o_ok$82 \fus_o_ok$134
-    connect \cu_wr__rel_o$83 \cu_wr__rel_o$61
-    connect \cu_wr__go_i$84 \cu_wr__go_i$62
-    connect \o_ok$85 \fus_o_ok$135
-    connect \cu_wr__rel_o$86 \cu_wr__rel_o$63
-    connect \cu_wr__go_i$87 \cu_wr__go_i$64
-    connect \cu_wr__rel_o$88 \cu_wr__rel_o$65
-    connect \cu_wr__go_i$89 \cu_wr__go_i$66
-    connect \dest1_o \dest1_o
-    connect \dest1_o$90 \dest1_o$67
-    connect \dest1_o$91 \dest1_o$68
-    connect \dest1_o$92 \dest1_o$69
-    connect \dest1_o$93 \dest1_o$70
-    connect \dest1_o$94 \dest1_o$71
-    connect \dest1_o$95 \dest1_o$72
-    connect \o \o
-    connect \ea \ea$73
+    connect \cu_wr__rel_o \fus_cu_wr__rel_o
+    connect \cu_wr__go_i \fus_cu_wr__go_i
+    connect \o_ok$70 \fus_o_ok$72
+    connect \cu_wr__rel_o$71 \fus_cu_wr__rel_o$73
+    connect \cu_wr__go_i$72 \fus_cu_wr__go_i$74
+    connect \o_ok$73 \fus_o_ok$75
+    connect \cu_wr__rel_o$74 \fus_cu_wr__rel_o$76
+    connect \cu_wr__go_i$75 \fus_cu_wr__go_i$77
+    connect \o_ok$76 \fus_o_ok$78
+    connect \cu_wr__rel_o$77 \fus_cu_wr__rel_o$79
+    connect \cu_wr__go_i$78 \fus_cu_wr__go_i$80
+    connect \o_ok$79 \fus_o_ok$81
+    connect \cu_wr__rel_o$80 \fus_cu_wr__rel_o$82
+    connect \cu_wr__go_i$81 \fus_cu_wr__go_i$83
+    connect \o_ok$82 \fus_o_ok$84
+    connect \cu_wr__rel_o$83 \fus_cu_wr__rel_o$85
+    connect \cu_wr__go_i$84 \fus_cu_wr__go_i$86
+    connect \o_ok$85 \fus_o_ok$87
+    connect \cu_wr__rel_o$86 \fus_cu_wr__rel_o$88
+    connect \cu_wr__go_i$87 \fus_cu_wr__go_i$89
+    connect \cu_wr__rel_o$88 \fus_cu_wr__rel_o$90
+    connect \cu_wr__go_i$89 \fus_cu_wr__go_i$91
+    connect \dest1_o \fus_dest1_o
+    connect \dest1_o$90 \fus_dest1_o$92
+    connect \dest1_o$91 \fus_dest1_o$93
+    connect \dest1_o$92 \fus_dest1_o$94
+    connect \dest1_o$93 \fus_dest1_o$95
+    connect \dest1_o$94 \fus_dest1_o$96
+    connect \dest1_o$95 \fus_dest1_o$97
+    connect \o \fus_o
+    connect \ea \fus_ea
     connect \full_cr_ok \fus_full_cr_ok
     connect \dest2_o \fus_dest2_o
     connect \cr_a_ok \fus_cr_a_ok
-    connect \cr_a_ok$96 \fus_cr_a_ok$136
-    connect \cr_a_ok$97 \fus_cr_a_ok$137
-    connect \cr_a_ok$98 \fus_cr_a_ok$138
-    connect \cr_a_ok$99 \fus_cr_a_ok$139
-    connect \dest2_o$100 \fus_dest2_o$140
+    connect \cr_a_ok$96 \fus_cr_a_ok$98
+    connect \cr_a_ok$97 \fus_cr_a_ok$99
+    connect \cr_a_ok$98 \fus_cr_a_ok$100
+    connect \cr_a_ok$99 \fus_cr_a_ok$101
+    connect \dest2_o$100 \fus_dest2_o$102
     connect \dest3_o \fus_dest3_o
-    connect \dest2_o$101 \fus_dest2_o$141
-    connect \dest2_o$102 \fus_dest2_o$142
-    connect \dest2_o$103 \fus_dest2_o$143
+    connect \dest2_o$101 \fus_dest2_o$103
+    connect \dest2_o$102 \fus_dest2_o$104
+    connect \dest2_o$103 \fus_dest2_o$105
     connect \xer_ca_ok \fus_xer_ca_ok
-    connect \xer_ca_ok$104 \fus_xer_ca_ok$144
-    connect \xer_ca_ok$105 \fus_xer_ca_ok$145
-    connect \xer_ca_ok$106 \fus_xer_ca_ok$146
-    connect \dest3_o$107 \fus_dest3_o$147
-    connect \dest3_o$108 \fus_dest3_o$148
+    connect \xer_ca_ok$104 \fus_xer_ca_ok$106
+    connect \xer_ca_ok$105 \fus_xer_ca_ok$107
+    connect \xer_ca_ok$106 \fus_xer_ca_ok$108
+    connect \dest3_o$107 \fus_dest3_o$109
+    connect \dest3_o$108 \fus_dest3_o$110
     connect \dest6_o \fus_dest6_o
-    connect \dest3_o$109 \fus_dest3_o$149
+    connect \dest3_o$109 \fus_dest3_o$111
     connect \xer_ov_ok \fus_xer_ov_ok
-    connect \xer_ov_ok$110 \fus_xer_ov_ok$150
-    connect \xer_ov_ok$111 \fus_xer_ov_ok$151
+    connect \xer_ov_ok$110 \fus_xer_ov_ok$112
+    connect \xer_ov_ok$111 \fus_xer_ov_ok$113
     connect \dest4_o \fus_dest4_o
     connect \dest5_o \fus_dest5_o
-    connect \dest3_o$112 \fus_dest3_o$152
+    connect \dest3_o$112 \fus_dest3_o$114
     connect \xer_so_ok \fus_xer_so_ok
-    connect \xer_so_ok$113 \fus_xer_so_ok$153
-    connect \xer_so_ok$114 \fus_xer_so_ok$154
-    connect \dest5_o$115 \fus_dest5_o$155
-    connect \dest4_o$116 \fus_dest4_o$156
-    connect \dest4_o$117 \fus_dest4_o$157
+    connect \xer_so_ok$113 \fus_xer_so_ok$115
+    connect \xer_so_ok$114 \fus_xer_so_ok$116
+    connect \dest5_o$115 \fus_dest5_o$117
+    connect \dest4_o$116 \fus_dest4_o$118
+    connect \dest4_o$117 \fus_dest4_o$119
     connect \fast1_ok \fus_fast1_ok
-    connect \cu_wr__rel_o$118 \cu_wr__rel_o$74
-    connect \cu_wr__go_i$119 \cu_wr__go_i$75
-    connect \fast1_ok$120 \fus_fast1_ok$158
-    connect \fast1_ok$121 \fus_fast1_ok$159
-    connect \dest1_o$122 \dest1_o$76
-    connect \dest2_o$123 \fus_dest2_o$160
-    connect \dest3_o$124 \fus_dest3_o$161
+    connect \cu_wr__rel_o$118 \fus_cu_wr__rel_o$120
+    connect \cu_wr__go_i$119 \fus_cu_wr__go_i$121
+    connect \fast1_ok$120 \fus_fast1_ok$122
+    connect \fast1_ok$121 \fus_fast1_ok$123
+    connect \dest1_o$122 \fus_dest1_o$124
+    connect \dest2_o$123 \fus_dest2_o$125
+    connect \dest3_o$124 \fus_dest3_o$126
     connect \fast2_ok \fus_fast2_ok
-    connect \fast2_ok$125 \fus_fast2_ok$162
-    connect \dest2_o$126 \fus_dest2_o$163
-    connect \dest3_o$127 \fus_dest3_o$164
+    connect \fast2_ok$125 \fus_fast2_ok$127
+    connect \dest2_o$126 \fus_dest2_o$128
+    connect \dest3_o$127 \fus_dest3_o$129
     connect \nia_ok \fus_nia_ok
-    connect \nia_ok$128 \fus_nia_ok$165
-    connect \dest3_o$129 \fus_dest3_o$166
-    connect \dest4_o$130 \fus_dest4_o$167
+    connect \nia_ok$128 \fus_nia_ok$130
+    connect \dest3_o$129 \fus_dest3_o$131
+    connect \dest4_o$130 \fus_dest4_o$132
     connect \msr_ok \fus_msr_ok
-    connect \dest5_o$131 \fus_dest5_o$168
+    connect \dest5_o$131 \fus_dest5_o$133
     connect \spr1_ok \fus_spr1_ok
-    connect \dest2_o$132 \fus_dest2_o$169
-    connect \cu_go_die_i \cu_go_die_i
-    connect \cu_shadown_i \cu_shadown_i
-    connect \cu_go_die_i$133 \cu_go_die_i$81
-    connect \cu_shadown_i$134 \cu_shadown_i$82
-    connect \cu_go_die_i$135 \cu_go_die_i$83
-    connect \cu_shadown_i$136 \cu_shadown_i$84
-    connect \cu_go_die_i$137 \cu_go_die_i$85
-    connect \cu_shadown_i$138 \cu_shadown_i$86
-    connect \cu_go_die_i$139 \cu_go_die_i$87
-    connect \cu_shadown_i$140 \cu_shadown_i$88
-    connect \cu_go_die_i$141 \cu_go_die_i$89
-    connect \cu_shadown_i$142 \cu_shadown_i$90
-    connect \cu_go_die_i$143 \cu_go_die_i$91
-    connect \cu_shadown_i$144 \cu_shadown_i$92
-    connect \cu_go_die_i$145 \cu_go_die_i$93
-    connect \cu_shadown_i$146 \cu_shadown_i$94
-    connect \cu_go_die_i$147 \cu_go_die_i$95
-    connect \load_mem_o \load_mem_o
-    connect \stwd_mem_o \stwd_mem_o
-    connect \cu_shadown_i$148 \cu_shadown_i$96
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
-    connect \ldst_port0_data_len \ldst_port0_data_len
-    connect \ldst_port0_addr_i \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+    connect \dest2_o$132 \fus_dest2_o$134
+    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \fus_ldst_port0_data_len
+    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
   end
   cell \l0 \l0
     connect \rst \rst
     connect \clk \clk
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
-    connect \ldst_port0_data_len \ldst_port0_data_len
-    connect \ldst_port0_addr_i \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
-    connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$97
-    connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$98
-    connect \ldst_port0_data_len$3 \ldst_port0_data_len$99
-    connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$100
-    connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$101
+    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \fus_ldst_port0_data_len
+    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
     connect \x_mask_i \x_mask_i
     connect \x_addr_i \x_addr_i
-    connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$102
     connect \m_ld_data_o \m_ld_data_o
-    connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$103
-    connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$104
     connect \x_busy_o \x_busy_o
-    connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$105
-    connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$106
     connect \x_st_data_i \x_st_data_i
-    connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$107
     connect \x_ld_i \x_ld_i
     connect \x_st_i \x_st_i
     connect \m_valid_i \m_valid_i
     connect \x_valid_i \x_valid_i
-    connect \ldst_port0_go_die_i \ldst_port0_go_die_i
-    connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$108
-    connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$109
     connect \dbus__cyc \dbus__cyc
     connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
@@ -149521,9 +149059,9 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \int_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen$170
+  wire width 32 \int_wen$135
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i$171
+  wire width 64 \int_data_i$136
   cell \int \int
     connect \rst \rst
     connect \clk \clk
@@ -149535,8 +149073,8 @@ module \core
     connect \src3__data_o \int_src3__data_o
     connect \wen \int_wen
     connect \data_i \int_data_i
-    connect \wen$1 \int_wen$170
-    connect \data_i$2 \int_data_i$171
+    connect \wen$1 \int_wen$135
+    connect \data_i$2 \int_data_i$136
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \cr_full_rd__ren
@@ -149595,13 +149133,13 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 2 \xer_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$172
+  wire width 3 \xer_wen$137
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$173
+  wire width 2 \xer_data_i$138
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$174
+  wire width 3 \xer_wen$139
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$175
+  wire width 2 \xer_data_i$140
   cell \xer \xer
     connect \rst \rst
     connect \clk \clk
@@ -149613,10 +149151,10 @@ module \core
     connect \src3__data_o \xer_src3__data_o
     connect \wen \xer_wen
     connect \data_i \xer_data_i
-    connect \wen$1 \xer_wen$172
-    connect \data_i$2 \xer_data_i$173
-    connect \wen$3 \xer_wen$174
-    connect \data_i$4 \xer_data_i$175
+    connect \wen$1 \xer_wen$137
+    connect \data_i$2 \xer_data_i$138
+    connect \wen$3 \xer_wen$139
+    connect \data_i$4 \xer_data_i$140
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \fast_src1__ren
@@ -149631,15 +149169,15 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \fast_data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$176
+  wire width 8 \fast_wen$141
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$177
+  wire width 64 \fast_data_i$142
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$178
+  wire width 64 \fast_data_i$143
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$179
+  wire width 8 \fast_wen$144
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$180
+  wire width 64 \fast_data_i$145
   cell \fast \fast
     connect \cia__ren \cia__ren
     connect \cia__data_o \cia__data_o
@@ -149656,11 +149194,11 @@ module \core
     connect \src2__data_o \fast_src2__data_o
     connect \wen$1 \fast_wen
     connect \data_i$2 \fast_data_i
-    connect \wen$3 \fast_wen$176
-    connect \data_i$4 \fast_data_i$177
-    connect \data_i$5 \fast_data_i$178
-    connect \wen$6 \fast_wen$179
-    connect \data_i$7 \fast_data_i$180
+    connect \wen$3 \fast_wen$141
+    connect \data_i$4 \fast_data_i$142
+    connect \data_i$5 \fast_data_i$143
+    connect \wen$6 \fast_wen$144
+    connect \data_i$7 \fast_data_i$145
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \spr_src__ren
@@ -150007,61 +149545,61 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  wire width 1 $181
+  wire width 1 $146
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  cell $not $182
+  cell $not $147
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_stopped
-    connect \Y $181
+    connect \Y $146
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  wire width 1 $183
+  wire width 1 $148
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  cell $and $184
+  cell $and $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \valid
-    connect \B $181
-    connect \Y $183
+    connect \B $146
+    connect \Y $148
   end
   process $group_2
     assign \can_run 1'0
-    assign \can_run $183
+    assign \can_run $148
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
   wire width 1 \en_alu0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $185
+  wire width 1 $150
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $186
+  wire width 11 $151
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $187
+  cell $and $152
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 2'10
-    connect \Y $186
+    connect \Y $151
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $188
+  cell $reduce_bool $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $186
-    connect \Y $185
+    connect \A $151
+    connect \Y $150
   end
   process $group_3
     assign \en_alu0 1'0
-    assign \en_alu0 $185
+    assign \en_alu0 $150
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:135"
@@ -150096,227 +149634,227 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $189
+  wire width 1 $154
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $190
+  wire width 11 $155
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $191
+  cell $and $156
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 7'1000000
-    connect \Y $190
+    connect \Y $155
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $192
+  cell $reduce_bool $157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $190
-    connect \Y $189
+    connect \A $155
+    connect \Y $154
   end
   process $group_5
     assign \en_cr0 1'0
-    assign \en_cr0 $189
+    assign \en_cr0 $154
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $193
+  wire width 1 $158
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $194
+  wire width 11 $159
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $195
+  cell $and $160
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 6
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 6'100000
-    connect \Y $194
+    connect \Y $159
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $196
+  cell $reduce_bool $161
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $194
-    connect \Y $193
+    connect \A $159
+    connect \Y $158
   end
   process $group_6
     assign \en_branch0 1'0
-    assign \en_branch0 $193
+    assign \en_branch0 $158
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $197
+  wire width 1 $162
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $198
+  wire width 11 $163
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $199
+  cell $and $164
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 8
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 8'10000000
-    connect \Y $198
+    connect \Y $163
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $200
+  cell $reduce_bool $165
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $198
-    connect \Y $197
+    connect \A $163
+    connect \Y $162
   end
   process $group_7
     assign \en_trap0 1'0
-    assign \en_trap0 $197
+    assign \en_trap0 $162
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $201
+  wire width 1 $166
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $202
+  wire width 11 $167
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $203
+  cell $and $168
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 5'10000
-    connect \Y $202
+    connect \Y $167
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $204
+  cell $reduce_bool $169
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $202
-    connect \Y $201
+    connect \A $167
+    connect \Y $166
   end
   process $group_8
     assign \en_logical0 1'0
-    assign \en_logical0 $201
+    assign \en_logical0 $166
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $205
+  wire width 1 $170
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $206
+  wire width 11 $171
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $207
+  cell $and $172
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 11
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 11'10000000000
-    connect \Y $206
+    connect \Y $171
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $208
+  cell $reduce_bool $173
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $206
-    connect \Y $205
+    connect \A $171
+    connect \Y $170
   end
   process $group_9
     assign \en_spr0 1'0
-    assign \en_spr0 $205
+    assign \en_spr0 $170
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $209
+  wire width 1 $174
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $210
+  wire width 11 $175
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $211
+  cell $and $176
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 9
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 9'100000000
-    connect \Y $210
+    connect \Y $175
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $212
+  cell $reduce_bool $177
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $210
-    connect \Y $209
+    connect \A $175
+    connect \Y $174
   end
   process $group_10
     assign \en_mul0 1'0
-    assign \en_mul0 $209
+    assign \en_mul0 $174
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $213
+  wire width 1 $178
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $214
+  wire width 11 $179
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $215
+  cell $and $180
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 4'1000
-    connect \Y $214
+    connect \Y $179
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $216
+  cell $reduce_bool $181
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $214
-    connect \Y $213
+    connect \A $179
+    connect \Y $178
   end
   process $group_11
     assign \en_shiftrot0 1'0
-    assign \en_shiftrot0 $213
+    assign \en_shiftrot0 $178
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $217
+  wire width 1 $182
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $218
+  wire width 11 $183
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $219
+  cell $and $184
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 11
-    connect \A \fn_unit
+    connect \A \pdecode2_fn_unit
     connect \B 3'100
-    connect \Y $218
+    connect \Y $183
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $220
+  cell $reduce_bool $185
     parameter \A_SIGNED 0
     parameter \A_WIDTH 11
     parameter \Y_WIDTH 1
-    connect \A $218
-    connect \Y $217
+    connect \A $183
+    connect \Y $182
   end
   process $group_12
     assign \en_ldst0 1'0
-    assign \en_ldst0 $217
+    assign \en_ldst0 $182
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
@@ -150324,9 +149862,9 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
   wire width 2 \counter$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 1 $221
+  wire width 1 $186
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  cell $ne $222
+  cell $ne $187
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150334,14 +149872,14 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \counter
     connect \B 1'0
-    connect \Y $221
+    connect \Y $186
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  wire width 3 $223
+  wire width 3 $188
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  wire width 3 $224
+  wire width 3 $189
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  cell $sub $225
+  cell $sub $190
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150349,16 +149887,16 @@ module \core
     parameter \Y_WIDTH 3
     connect \A \counter
     connect \B 1'1
-    connect \Y $224
+    connect \Y $189
   end
-  connect $223 $224
+  connect $188 $189
   process $group_13
     assign \counter$next \counter
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-    switch { $221 }
+    switch { $186 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
       case 1'1
-        assign \counter$next $223 [1:0]
+        assign \counter$next $188 [1:0]
     end
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
@@ -150389,9 +149927,9 @@ module \core
       update \counter \counter$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 1 $226
+  wire width 1 $191
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  cell $ne $227
+  cell $ne $192
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
@@ -150399,12 +149937,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \counter
     connect \B 1'0
-    connect \Y $226
+    connect \Y $191
   end
   process $group_14
     assign \corebusy_o 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-    switch { $226 }
+    switch { $191 }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
       case 1'1
         assign \corebusy_o 1'1
@@ -150429,62 +149967,62 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o
+                assign \corebusy_o \fus_cu_busy_o
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$2
+                assign \corebusy_o \fus_cu_busy_o$4
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$6
+                assign \corebusy_o \fus_cu_busy_o$7
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$9
+                assign \corebusy_o \fus_cu_busy_o$10
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$11
+                assign \corebusy_o \fus_cu_busy_o$13
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$13
+                assign \corebusy_o \fus_cu_busy_o$16
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$15
+                assign \corebusy_o \fus_cu_busy_o$19
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$17
+                assign \corebusy_o \fus_cu_busy_o$22
             end
             attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \corebusy_o \cu_busy_o$19
+                assign \corebusy_o \fus_cu_busy_o$25
             end
         end
     end
     sync init
   end
   process $group_15
-    assign \oper_i_alu_alu0__insn_type 7'0000000
+    assign \fus_oper_i_alu_alu0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150504,14 +150042,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__insn_type \insn_type
+                assign \fus_oper_i_alu_alu0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_16
-    assign \oper_i_alu_alu0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150531,7 +150069,7 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit
             end
         end
     end
@@ -150559,7 +150097,7 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
@@ -150587,7 +150125,7 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
@@ -150615,14 +150153,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
   process $group_23
-    assign \oper_i_alu_alu0__invert_a 1'0
+    assign \fus_oper_i_alu_alu0__invert_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150642,14 +150180,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__invert_a \invert_a
+                assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a
             end
         end
     end
     sync init
   end
   process $group_24
-    assign \oper_i_alu_alu0__zero_a 1'0
+    assign \fus_oper_i_alu_alu0__zero_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150669,14 +150207,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__zero_a \zero_a
+                assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a
             end
         end
     end
     sync init
   end
   process $group_25
-    assign \oper_i_alu_alu0__invert_out 1'0
+    assign \fus_oper_i_alu_alu0__invert_out 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150696,14 +150234,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__invert_out \invert_out
+                assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out
             end
         end
     end
     sync init
   end
   process $group_26
-    assign \oper_i_alu_alu0__write_cr0 1'0
+    assign \fus_oper_i_alu_alu0__write_cr0 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150723,14 +150261,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__write_cr0 \write_cr0
+                assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0
             end
         end
     end
     sync init
   end
   process $group_27
-    assign \oper_i_alu_alu0__input_carry 2'00
+    assign \fus_oper_i_alu_alu0__input_carry 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150750,14 +150288,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__input_carry \input_carry
+                assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry
             end
         end
     end
     sync init
   end
   process $group_28
-    assign \oper_i_alu_alu0__output_carry 1'0
+    assign \fus_oper_i_alu_alu0__output_carry 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150777,14 +150315,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__output_carry \output_carry
+                assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry
             end
         end
     end
     sync init
   end
   process $group_29
-    assign \oper_i_alu_alu0__is_32bit 1'0
+    assign \fus_oper_i_alu_alu0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150804,14 +150342,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_30
-    assign \oper_i_alu_alu0__is_signed 1'0
+    assign \fus_oper_i_alu_alu0__is_signed 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150831,14 +150369,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__is_signed \is_signed
+                assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
   process $group_31
-    assign \oper_i_alu_alu0__data_len 4'0000
+    assign \fus_oper_i_alu_alu0__data_len 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150858,14 +150396,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__data_len \data_len
+                assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
   process $group_32
-    assign \oper_i_alu_alu0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150885,14 +150423,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_alu0__insn \insn
+                assign \fus_oper_i_alu_alu0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_33
-    assign \cu_issue_i 1'0
+    assign \fus_cu_issue_i 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -150912,73 +150450,73 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i \issue_i
+                assign \fus_cu_issue_i \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $228
+  wire width 4 $193
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $229
+  wire width 1 $194
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $230
+  cell $and $195
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $229
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $194
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $231
+  wire width 1 $196
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $232
+  cell $or $197
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $229
-    connect \B \xer_in
-    connect \Y $231
+    connect \A $194
+    connect \B \pdecode2_xer_in
+    connect \Y $196
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $233
+  wire width 1 $198
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $234
+  cell $eq $199
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \input_carry
+    connect \A \pdecode2_input_carry
     connect \B 2'10
-    connect \Y $233
+    connect \Y $198
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $235
+  wire width 1 $200
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $236
+  cell $or $201
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $233
-    connect \B \xer_in
-    connect \Y $235
+    connect \A $198
+    connect \B \pdecode2_xer_in
+    connect \Y $200
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $237
+  cell $not $202
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A { $235 $231 \reg2_ok \reg1_ok }
-    connect \Y $228
+    connect \A { $200 $196 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $193
   end
   process $group_34
     assign \fus_cu_rdmaskn_i 4'0000
@@ -151001,14 +150539,14 @@ module \core
             switch { \fu_enable [0] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i $228
+                assign \fus_cu_rdmaskn_i $193
             end
         end
     end
     sync init
   end
   process $group_35
-    assign \oper_i_alu_cr0__insn_type 7'0000000
+    assign \fus_oper_i_alu_cr0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151028,14 +150566,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_cr0__insn_type \insn_type
+                assign \fus_oper_i_alu_cr0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_36
-    assign \oper_i_alu_cr0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151055,14 +150593,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_cr0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
   process $group_37
-    assign \oper_i_alu_cr0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151082,14 +150620,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_cr0__insn \insn
+                assign \fus_oper_i_alu_cr0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_38
-    assign \oper_i_alu_cr0__read_cr_whole 1'0
+    assign \fus_oper_i_alu_cr0__read_cr_whole 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151109,14 +150647,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_cr0__read_cr_whole \read_cr_whole
+                assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole
             end
         end
     end
     sync init
   end
   process $group_39
-    assign \oper_i_alu_cr0__write_cr_whole 1'0
+    assign \fus_oper_i_alu_cr0__write_cr_whole 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151136,14 +150674,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_cr0__write_cr_whole \write_cr_whole
+                assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole
             end
         end
     end
     sync init
   end
   process $group_40
-    assign \cu_issue_i$1 1'0
+    assign \fus_cu_issue_i$3 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151163,24 +150701,24 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$1 \issue_i
+                assign \fus_cu_issue_i$3 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 6 $238
+  wire width 6 $203
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $239
+  cell $not $204
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A { \cr_in2_ok$3 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
-    connect \Y $238
+    connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $203
   end
   process $group_41
-    assign \fus_cu_rdmaskn_i$110 6'000000
+    assign \fus_cu_rdmaskn_i$5 6'000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151200,14 +150738,14 @@ module \core
             switch { \fu_enable [1] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$110 $238
+                assign \fus_cu_rdmaskn_i$5 $203
             end
         end
     end
     sync init
   end
   process $group_42
-    assign \oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151227,14 +150765,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__cia \cia$4
+                assign \fus_oper_i_alu_branch0__cia \pdecode2_cia
             end
         end
     end
     sync init
   end
   process $group_43
-    assign \oper_i_alu_branch0__insn_type 7'0000000
+    assign \fus_oper_i_alu_branch0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151254,14 +150792,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__insn_type \insn_type
+                assign \fus_oper_i_alu_branch0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_44
-    assign \oper_i_alu_branch0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151281,14 +150819,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
   process $group_45
-    assign \oper_i_alu_branch0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151308,7 +150846,7 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__insn \insn
+                assign \fus_oper_i_alu_branch0__insn \pdecode2_insn
             end
         end
     end
@@ -151336,14 +150874,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
   process $group_48
-    assign \oper_i_alu_branch0__lk 1'0
+    assign \fus_oper_i_alu_branch0__lk 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151363,14 +150901,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__lk \lk
+                assign \fus_oper_i_alu_branch0__lk \pdecode2_lk
             end
         end
     end
     sync init
   end
   process $group_49
-    assign \oper_i_alu_branch0__is_32bit 1'0
+    assign \fus_oper_i_alu_branch0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151390,14 +150928,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_branch0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_50
-    assign \cu_issue_i$5 1'0
+    assign \fus_cu_issue_i$6 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151417,24 +150955,24 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$5 \issue_i
+                assign \fus_cu_issue_i$6 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $240
+  wire width 3 $205
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $241
+  cell $not $206
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A { \cr_in1_ok \fast2_ok \fast1_ok }
-    connect \Y $240
+    connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
+    connect \Y $205
   end
   process $group_51
-    assign \fus_cu_rdmaskn_i$111 3'000
+    assign \fus_cu_rdmaskn_i$8 3'000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151454,14 +150992,14 @@ module \core
             switch { \fu_enable [2] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$111 $240
+                assign \fus_cu_rdmaskn_i$8 $205
             end
         end
     end
     sync init
   end
   process $group_52
-    assign \oper_i_alu_trap0__insn_type 7'0000000
+    assign \fus_oper_i_alu_trap0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151481,14 +151019,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__insn_type \insn_type
+                assign \fus_oper_i_alu_trap0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_53
-    assign \oper_i_alu_trap0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151508,14 +151046,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
   process $group_54
-    assign \oper_i_alu_trap0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151535,14 +151073,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__insn \insn
+                assign \fus_oper_i_alu_trap0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_55
-    assign \oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151562,14 +151100,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__msr \msr$7
+                assign \fus_oper_i_alu_trap0__msr \pdecode2_msr
             end
         end
     end
     sync init
   end
   process $group_56
-    assign \oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151589,14 +151127,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__cia \cia$4
+                assign \fus_oper_i_alu_trap0__cia \pdecode2_cia
             end
         end
     end
     sync init
   end
   process $group_57
-    assign \oper_i_alu_trap0__is_32bit 1'0
+    assign \fus_oper_i_alu_trap0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151616,14 +151154,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_58
-    assign \oper_i_alu_trap0__traptype 5'00000
+    assign \fus_oper_i_alu_trap0__traptype 5'00000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151643,14 +151181,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__traptype \traptype
+                assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype
             end
         end
     end
     sync init
   end
   process $group_59
-    assign \oper_i_alu_trap0__trapaddr 13'0000000000000
+    assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151670,14 +151208,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_trap0__trapaddr \trapaddr
+                assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr
             end
         end
     end
     sync init
   end
   process $group_60
-    assign \cu_issue_i$8 1'0
+    assign \fus_cu_issue_i$9 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151697,24 +151235,24 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$8 \issue_i
+                assign \fus_cu_issue_i$9 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $242
+  wire width 4 $207
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $243
+  cell $not $208
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A { \fast2_ok \fast1_ok \reg2_ok \reg1_ok }
-    connect \Y $242
+    connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $207
   end
   process $group_61
-    assign \fus_cu_rdmaskn_i$112 4'0000
+    assign \fus_cu_rdmaskn_i$11 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151734,14 +151272,14 @@ module \core
             switch { \fu_enable [3] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$112 $242
+                assign \fus_cu_rdmaskn_i$11 $207
             end
         end
     end
     sync init
   end
   process $group_62
-    assign \oper_i_alu_logical0__insn_type 7'0000000
+    assign \fus_oper_i_alu_logical0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151761,14 +151299,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__insn_type \insn_type
+                assign \fus_oper_i_alu_logical0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_63
-    assign \oper_i_alu_logical0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151788,7 +151326,7 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit
             end
         end
     end
@@ -151816,7 +151354,7 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
@@ -151844,7 +151382,7 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
@@ -151872,14 +151410,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
   process $group_70
-    assign \oper_i_alu_logical0__invert_a 1'0
+    assign \fus_oper_i_alu_logical0__invert_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151899,14 +151437,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__invert_a \invert_a
+                assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a
             end
         end
     end
     sync init
   end
   process $group_71
-    assign \oper_i_alu_logical0__zero_a 1'0
+    assign \fus_oper_i_alu_logical0__zero_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151926,14 +151464,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__zero_a \zero_a
+                assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a
             end
         end
     end
     sync init
   end
   process $group_72
-    assign \oper_i_alu_logical0__input_carry 2'00
+    assign \fus_oper_i_alu_logical0__input_carry 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151953,14 +151491,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__input_carry \input_carry
+                assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry
             end
         end
     end
     sync init
   end
   process $group_73
-    assign \oper_i_alu_logical0__invert_out 1'0
+    assign \fus_oper_i_alu_logical0__invert_out 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -151980,14 +151518,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__invert_out \invert_out
+                assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out
             end
         end
     end
     sync init
   end
   process $group_74
-    assign \oper_i_alu_logical0__write_cr0 1'0
+    assign \fus_oper_i_alu_logical0__write_cr0 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152007,14 +151545,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__write_cr0 \write_cr0
+                assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0
             end
         end
     end
     sync init
   end
   process $group_75
-    assign \oper_i_alu_logical0__output_carry 1'0
+    assign \fus_oper_i_alu_logical0__output_carry 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152034,14 +151572,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__output_carry \output_carry
+                assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry
             end
         end
     end
     sync init
   end
   process $group_76
-    assign \oper_i_alu_logical0__is_32bit 1'0
+    assign \fus_oper_i_alu_logical0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152061,14 +151599,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_77
-    assign \oper_i_alu_logical0__is_signed 1'0
+    assign \fus_oper_i_alu_logical0__is_signed 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152088,14 +151626,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__is_signed \is_signed
+                assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
   process $group_78
-    assign \oper_i_alu_logical0__data_len 4'0000
+    assign \fus_oper_i_alu_logical0__data_len 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152115,14 +151653,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__data_len \data_len
+                assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
   process $group_79
-    assign \oper_i_alu_logical0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152142,14 +151680,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_logical0__insn \insn
+                assign \fus_oper_i_alu_logical0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_80
-    assign \cu_issue_i$10 1'0
+    assign \fus_cu_issue_i$12 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152169,24 +151707,24 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$10 \issue_i
+                assign \fus_cu_issue_i$12 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 2 $244
+  wire width 2 $209
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $245
+  cell $not $210
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A { \reg2_ok \reg1_ok }
-    connect \Y $244
+    connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $209
   end
   process $group_81
-    assign \fus_cu_rdmaskn_i$113 2'00
+    assign \fus_cu_rdmaskn_i$14 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152206,14 +151744,14 @@ module \core
             switch { \fu_enable [4] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$113 $244
+                assign \fus_cu_rdmaskn_i$14 $209
             end
         end
     end
     sync init
   end
   process $group_82
-    assign \oper_i_alu_spr0__insn_type 7'0000000
+    assign \fus_oper_i_alu_spr0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152233,14 +151771,14 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_spr0__insn_type \insn_type
+                assign \fus_oper_i_alu_spr0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_83
-    assign \oper_i_alu_spr0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152260,14 +151798,14 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_spr0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
   process $group_84
-    assign \oper_i_alu_spr0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152287,14 +151825,14 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_spr0__insn \insn
+                assign \fus_oper_i_alu_spr0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_85
-    assign \oper_i_alu_spr0__is_32bit 1'0
+    assign \fus_oper_i_alu_spr0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152314,14 +151852,14 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_spr0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_86
-    assign \cu_issue_i$12 1'0
+    assign \fus_cu_issue_i$15 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152341,102 +151879,102 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$12 \issue_i
+                assign \fus_cu_issue_i$15 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 6 $246
+  wire width 6 $211
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $247
+  wire width 1 $212
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $248
+  cell $and $213
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $247
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $212
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $249
+  wire width 1 $214
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $250
+  cell $or $215
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $247
-    connect \B \xer_in
-    connect \Y $249
+    connect \A $212
+    connect \B \pdecode2_xer_in
+    connect \Y $214
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $251
+  wire width 1 $216
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $252
+  cell $and $217
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $251
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $216
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $253
+  wire width 1 $218
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $254
+  cell $or $219
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $251
-    connect \B \xer_in
-    connect \Y $253
+    connect \A $216
+    connect \B \pdecode2_xer_in
+    connect \Y $218
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $255
+  wire width 1 $220
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $256
+  cell $eq $221
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \input_carry
+    connect \A \pdecode2_input_carry
     connect \B 2'10
-    connect \Y $255
+    connect \Y $220
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $257
+  wire width 1 $222
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $258
+  cell $or $223
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $255
-    connect \B \xer_in
-    connect \Y $257
+    connect \A $220
+    connect \B \pdecode2_xer_in
+    connect \Y $222
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $259
+  cell $not $224
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 6
-    connect \A { $257 $253 $249 \fast1_ok \spr1_ok \reg1_ok }
-    connect \Y $246
+    connect \A { $222 $218 $214 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
+    connect \Y $211
   end
   process $group_87
-    assign \fus_cu_rdmaskn_i$114 6'000000
+    assign \fus_cu_rdmaskn_i$17 6'000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152456,14 +151994,14 @@ module \core
             switch { \fu_enable [5] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$114 $246
+                assign \fus_cu_rdmaskn_i$17 $211
             end
         end
     end
     sync init
   end
   process $group_88
-    assign \oper_i_alu_mul0__insn_type 7'0000000
+    assign \fus_oper_i_alu_mul0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152483,14 +152021,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__insn_type \insn_type
+                assign \fus_oper_i_alu_mul0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_89
-    assign \oper_i_alu_mul0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152510,7 +152048,7 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit
             end
         end
     end
@@ -152538,7 +152076,7 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
@@ -152566,7 +152104,7 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
@@ -152594,14 +152132,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
   process $group_96
-    assign \oper_i_alu_mul0__invert_a 1'0
+    assign \fus_oper_i_alu_mul0__invert_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152621,14 +152159,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__invert_a \invert_a
+                assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a
             end
         end
     end
     sync init
   end
   process $group_97
-    assign \oper_i_alu_mul0__zero_a 1'0
+    assign \fus_oper_i_alu_mul0__zero_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152648,14 +152186,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__zero_a \zero_a
+                assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a
             end
         end
     end
     sync init
   end
   process $group_98
-    assign \oper_i_alu_mul0__invert_out 1'0
+    assign \fus_oper_i_alu_mul0__invert_out 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152675,14 +152213,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__invert_out \invert_out
+                assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out
             end
         end
     end
     sync init
   end
   process $group_99
-    assign \oper_i_alu_mul0__write_cr0 1'0
+    assign \fus_oper_i_alu_mul0__write_cr0 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152702,14 +152240,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__write_cr0 \write_cr0
+                assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0
             end
         end
     end
     sync init
   end
   process $group_100
-    assign \oper_i_alu_mul0__is_32bit 1'0
+    assign \fus_oper_i_alu_mul0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152729,14 +152267,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_101
-    assign \oper_i_alu_mul0__is_signed 1'0
+    assign \fus_oper_i_alu_mul0__is_signed 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152756,14 +152294,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__is_signed \is_signed
+                assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
   process $group_102
-    assign \oper_i_alu_mul0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152783,14 +152321,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_mul0__insn \insn
+                assign \fus_oper_i_alu_mul0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_103
-    assign \cu_issue_i$14 1'0
+    assign \fus_cu_issue_i$18 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152810,50 +152348,50 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$14 \issue_i
+                assign \fus_cu_issue_i$18 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $260
+  wire width 3 $225
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $261
+  wire width 1 $226
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $262
+  cell $and $227
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $261
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $226
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $263
+  wire width 1 $228
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $264
+  cell $or $229
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $261
-    connect \B \xer_in
-    connect \Y $263
+    connect \A $226
+    connect \B \pdecode2_xer_in
+    connect \Y $228
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $265
+  cell $not $230
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A { $263 \reg2_ok \reg1_ok }
-    connect \Y $260
+    connect \A { $228 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $225
   end
   process $group_104
-    assign \fus_cu_rdmaskn_i$115 3'000
+    assign \fus_cu_rdmaskn_i$20 3'000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152873,14 +152411,14 @@ module \core
             switch { \fu_enable [6] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$115 $260
+                assign \fus_cu_rdmaskn_i$20 $225
             end
         end
     end
     sync init
   end
   process $group_105
-    assign \oper_i_alu_shift_rot0__insn_type 7'0000000
+    assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152900,14 +152438,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__insn_type \insn_type
+                assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type
             end
         end
     end
     sync init
   end
   process $group_106
-    assign \oper_i_alu_shift_rot0__fn_unit 11'00000000000
+    assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -152927,7 +152465,7 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__fn_unit \fn_unit
+                assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit
             end
         end
     end
@@ -152955,7 +152493,7 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
@@ -152983,7 +152521,7 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
@@ -153011,7 +152549,7 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
@@ -153045,7 +152583,7 @@ module \core
     sync init
   end
   process $group_114
-    assign \oper_i_alu_shift_rot0__input_carry 2'00
+    assign \fus_oper_i_alu_shift_rot0__input_carry 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153065,14 +152603,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__input_carry \input_carry
+                assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry
             end
         end
     end
     sync init
   end
   process $group_115
-    assign \oper_i_alu_shift_rot0__output_carry 1'0
+    assign \fus_oper_i_alu_shift_rot0__output_carry 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153092,14 +152630,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__output_carry \output_carry
+                assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry
             end
         end
     end
     sync init
   end
   process $group_116
-    assign \oper_i_alu_shift_rot0__input_cr 1'0
+    assign \fus_oper_i_alu_shift_rot0__input_cr 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153119,14 +152657,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__input_cr \input_cr
+                assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr
             end
         end
     end
     sync init
   end
   process $group_117
-    assign \oper_i_alu_shift_rot0__output_cr 1'0
+    assign \fus_oper_i_alu_shift_rot0__output_cr 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153146,14 +152684,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__output_cr \output_cr
+                assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr
             end
         end
     end
     sync init
   end
   process $group_118
-    assign \oper_i_alu_shift_rot0__is_32bit 1'0
+    assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153173,14 +152711,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__is_32bit \is_32bit
+                assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_119
-    assign \oper_i_alu_shift_rot0__is_signed 1'0
+    assign \fus_oper_i_alu_shift_rot0__is_signed 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153200,14 +152738,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__is_signed \is_signed
+                assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
   process $group_120
-    assign \oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
+    assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153227,14 +152765,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_alu_shift_rot0__insn \insn
+                assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
   process $group_121
-    assign \cu_issue_i$16 1'0
+    assign \fus_cu_issue_i$21 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153254,50 +152792,50 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$16 \issue_i
+                assign \fus_cu_issue_i$21 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $266
+  wire width 4 $231
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $267
+  wire width 1 $232
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $268
+  cell $eq $233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \input_carry
+    connect \A \pdecode2_input_carry
     connect \B 2'10
-    connect \Y $267
+    connect \Y $232
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $269
+  wire width 1 $234
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $270
+  cell $or $235
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $267
-    connect \B \xer_in
-    connect \Y $269
+    connect \A $232
+    connect \B \pdecode2_xer_in
+    connect \Y $234
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $271
+  cell $not $236
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A { $269 \reg3_ok \reg2_ok \reg1_ok }
-    connect \Y $266
+    connect \A { $234 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $231
   end
   process $group_122
-    assign \fus_cu_rdmaskn_i$116 4'0000
+    assign \fus_cu_rdmaskn_i$23 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153317,14 +152855,14 @@ module \core
             switch { \fu_enable [7] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$116 $266
+                assign \fus_cu_rdmaskn_i$23 $231
             end
         end
     end
     sync init
   end
   process $group_123
-    assign \oper_i_ldst_ldst0__insn_type 7'0000000
+    assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153344,7 +152882,7 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__insn_type \insn_type
+                assign \fus_oper_i_ldst_ldst0__insn_type \insn_type
             end
         end
     end
@@ -153372,14 +152910,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \imm_ok \imm }
+                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
   process $group_126
-    assign \oper_i_ldst_ldst0__zero_a 1'0
+    assign \fus_oper_i_ldst_ldst0__zero_a 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153399,7 +152937,7 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__zero_a \zero_a
+                assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a
             end
         end
     end
@@ -153427,7 +152965,7 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \rc_ok \rc }
+                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
@@ -153455,14 +152993,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \oe_ok \oe }
+                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
   process $group_131
-    assign \oper_i_ldst_ldst0__is_32bit 1'0
+    assign \fus_oper_i_ldst_ldst0__is_32bit 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153482,14 +153020,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__is_32bit \is_32bit
+                assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
   process $group_132
-    assign \oper_i_ldst_ldst0__is_signed 1'0
+    assign \fus_oper_i_ldst_ldst0__is_signed 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153509,14 +153047,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__is_signed \is_signed
+                assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
   process $group_133
-    assign \oper_i_ldst_ldst0__data_len 4'0000
+    assign \fus_oper_i_ldst_ldst0__data_len 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153536,14 +153074,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__data_len \data_len
+                assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
   process $group_134
-    assign \oper_i_ldst_ldst0__byte_reverse 1'0
+    assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153563,14 +153101,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__byte_reverse \byte_reverse
+                assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse
             end
         end
     end
     sync init
   end
   process $group_135
-    assign \oper_i_ldst_ldst0__sign_extend 1'0
+    assign \fus_oper_i_ldst_ldst0__sign_extend 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153590,14 +153128,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__sign_extend \sign_extend
+                assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend
             end
         end
     end
     sync init
   end
   process $group_136
-    assign \oper_i_ldst_ldst0__ldst_mode 2'00
+    assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153617,14 +153155,14 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \oper_i_ldst_ldst0__ldst_mode \ldst_mode
+                assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode
             end
         end
     end
     sync init
   end
   process $group_137
-    assign \cu_issue_i$18 1'0
+    assign \fus_cu_issue_i$24 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153644,24 +153182,24 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \cu_issue_i$18 \issue_i
+                assign \fus_cu_issue_i$24 \issue_i
             end
         end
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $272
+  wire width 3 $237
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $273
+  cell $not $238
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A { \reg3_ok \reg2_ok \reg1_ok }
-    connect \Y $272
+    connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $237
   end
   process $group_138
-    assign \fus_cu_rdmaskn_i$117 3'000
+    assign \fus_cu_rdmaskn_i$26 3'000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
     switch { \can_run }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
@@ -153681,7 +153219,7 @@ module \core
             switch { \fu_enable [8] }
               attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
               case 1'1
-                assign \fus_cu_rdmaskn_i$117 $272
+                assign \fus_cu_rdmaskn_i$26 $237
             end
         end
     end
@@ -153691,21 +153229,21 @@ module \core
   wire width 1 \rdflag_INT_ra
   process $group_139
     assign \rdflag_INT_ra 1'0
-    assign \rdflag_INT_ra \reg1_ok
+    assign \rdflag_INT_ra \pdecode2_reg1_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  wire width 32 $274
+  wire width 32 $239
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  cell $sshl $275
+  cell $sshl $240
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \reg1
-    connect \Y $274
+    connect \B \pdecode2_reg1
+    connect \Y $239
   end
   process $group_140
     assign \int_src1__ren 32'00000000000000000000000000000000
@@ -153713,353 +153251,353 @@ module \core
     switch { \rdpick_INT_ra_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src1__ren $274
+        assign \int_src1__ren $239
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $276
+  wire width 1 $241
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $277
+  cell $and $242
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [0]
+    connect \A \fus_cu_rd__rel_o [0]
     connect \B \fu_enable [0]
-    connect \Y $276
+    connect \Y $241
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $278
+  wire width 1 $243
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $279
+  cell $and $244
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $276
+    connect \A $241
     connect \B \rdflag_INT_ra
-    connect \Y $278
+    connect \Y $243
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $280
+  wire width 1 $245
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $281
+  cell $and $246
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [0]
+    connect \A \fus_cu_rd__rel_o$27 [0]
     connect \B \fu_enable [1]
-    connect \Y $280
+    connect \Y $245
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $282
+  wire width 1 $247
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $283
+  cell $and $248
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $280
+    connect \A $245
     connect \B \rdflag_INT_ra
-    connect \Y $282
+    connect \Y $247
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $284
+  wire width 1 $249
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $285
+  cell $and $250
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$23 [0]
+    connect \A \fus_cu_rd__rel_o$30 [0]
     connect \B \fu_enable [3]
-    connect \Y $284
+    connect \Y $249
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $286
+  wire width 1 $251
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $287
+  cell $and $252
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $284
+    connect \A $249
     connect \B \rdflag_INT_ra
-    connect \Y $286
+    connect \Y $251
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $288
+  wire width 1 $253
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $289
+  cell $and $254
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$26 [0]
+    connect \A \fus_cu_rd__rel_o$33 [0]
     connect \B \fu_enable [4]
-    connect \Y $288
+    connect \Y $253
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $290
+  wire width 1 $255
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $291
+  cell $and $256
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $288
+    connect \A $253
     connect \B \rdflag_INT_ra
-    connect \Y $290
+    connect \Y $255
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $292
+  wire width 1 $257
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $293
+  cell $and $258
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [0]
+    connect \A \fus_cu_rd__rel_o$36 [0]
     connect \B \fu_enable [5]
-    connect \Y $292
+    connect \Y $257
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $294
+  wire width 1 $259
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $295
+  cell $and $260
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $292
+    connect \A $257
     connect \B \rdflag_INT_ra
-    connect \Y $294
+    connect \Y $259
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $296
+  wire width 1 $261
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $297
+  cell $and $262
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$32 [0]
+    connect \A \fus_cu_rd__rel_o$39 [0]
     connect \B \fu_enable [6]
-    connect \Y $296
+    connect \Y $261
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $298
+  wire width 1 $263
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $299
+  cell $and $264
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $296
+    connect \A $261
     connect \B \rdflag_INT_ra
-    connect \Y $298
+    connect \Y $263
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $300
+  wire width 1 $265
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $301
+  cell $and $266
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$35 [0]
+    connect \A \fus_cu_rd__rel_o$42 [0]
     connect \B \fu_enable [7]
-    connect \Y $300
+    connect \Y $265
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $302
+  wire width 1 $267
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $303
+  cell $and $268
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $300
+    connect \A $265
     connect \B \rdflag_INT_ra
-    connect \Y $302
+    connect \Y $267
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $304
+  wire width 1 $269
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $305
+  cell $and $270
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$38 [0]
+    connect \A \fus_cu_rd__rel_o$45 [0]
     connect \B \fu_enable [8]
-    connect \Y $304
+    connect \Y $269
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $306
+  wire width 1 $271
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $307
+  cell $and $272
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $304
+    connect \A $269
     connect \B \rdflag_INT_ra
-    connect \Y $306
+    connect \Y $271
   end
   process $group_141
     assign \rdpick_INT_ra_i 8'00000000
-    assign \rdpick_INT_ra_i [0] $278
-    assign \rdpick_INT_ra_i [1] $282
-    assign \rdpick_INT_ra_i [2] $286
-    assign \rdpick_INT_ra_i [3] $290
-    assign \rdpick_INT_ra_i [4] $294
-    assign \rdpick_INT_ra_i [5] $298
-    assign \rdpick_INT_ra_i [6] $302
-    assign \rdpick_INT_ra_i [7] $306
+    assign \rdpick_INT_ra_i [0] $243
+    assign \rdpick_INT_ra_i [1] $247
+    assign \rdpick_INT_ra_i [2] $251
+    assign \rdpick_INT_ra_i [3] $255
+    assign \rdpick_INT_ra_i [4] $259
+    assign \rdpick_INT_ra_i [5] $263
+    assign \rdpick_INT_ra_i [6] $267
+    assign \rdpick_INT_ra_i [7] $271
     sync init
   end
   process $group_142
-    assign \cu_rd__go_i 4'0000
-    assign \cu_rd__go_i [0] \rdpick_INT_ra_o [0]
-    assign \cu_rd__go_i [1] \rdpick_INT_rb_o [0]
-    assign \cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
-    assign \cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
+    assign \fus_cu_rd__go_i 4'0000
+    assign \fus_cu_rd__go_i [0] \rdpick_INT_ra_o [0]
+    assign \fus_cu_rd__go_i [1] \rdpick_INT_rb_o [0]
+    assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
+    assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
     sync init
   end
   process $group_143
-    assign \src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i \int_src1__data_o
+    assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i \int_src1__data_o
     sync init
   end
   process $group_144
-    assign \cu_rd__go_i$21 6'000000
-    assign \cu_rd__go_i$21 [0] \rdpick_INT_ra_o [1]
-    assign \cu_rd__go_i$21 [1] \rdpick_INT_rb_o [1]
-    assign \cu_rd__go_i$21 [2] \rdpick_CR_full_cr_o
-    assign \cu_rd__go_i$21 [3] \rdpick_CR_cr_a_o [0]
-    assign \cu_rd__go_i$21 [4] \rdpick_CR_cr_b_o
-    assign \cu_rd__go_i$21 [5] \rdpick_CR_cr_c_o
+    assign \fus_cu_rd__go_i$28 6'000000
+    assign \fus_cu_rd__go_i$28 [0] \rdpick_INT_ra_o [1]
+    assign \fus_cu_rd__go_i$28 [1] \rdpick_INT_rb_o [1]
+    assign \fus_cu_rd__go_i$28 [2] \rdpick_CR_full_cr_o
+    assign \fus_cu_rd__go_i$28 [3] \rdpick_CR_cr_a_o [0]
+    assign \fus_cu_rd__go_i$28 [4] \rdpick_CR_cr_b_o
+    assign \fus_cu_rd__go_i$28 [5] \rdpick_CR_cr_c_o
     sync init
   end
   process $group_145
-    assign \src1_i$22 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$22 \int_src1__data_o
+    assign \fus_src1_i$29 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$29 \int_src1__data_o
     sync init
   end
   process $group_146
-    assign \cu_rd__go_i$24 4'0000
-    assign \cu_rd__go_i$24 [0] \rdpick_INT_ra_o [2]
-    assign \cu_rd__go_i$24 [1] \rdpick_INT_rb_o [2]
-    assign \cu_rd__go_i$24 [2] \rdpick_FAST_fast1_o [1]
-    assign \cu_rd__go_i$24 [3] \rdpick_FAST_fast2_o [1]
+    assign \fus_cu_rd__go_i$31 4'0000
+    assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [2]
+    assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rb_o [2]
+    assign \fus_cu_rd__go_i$31 [2] \rdpick_FAST_fast1_o [1]
+    assign \fus_cu_rd__go_i$31 [3] \rdpick_FAST_fast2_o [1]
     sync init
   end
   process $group_147
-    assign \src1_i$25 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$25 \int_src1__data_o
+    assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$32 \int_src1__data_o
     sync init
   end
   process $group_148
-    assign \cu_rd__go_i$27 2'00
-    assign \cu_rd__go_i$27 [0] \rdpick_INT_ra_o [3]
-    assign \cu_rd__go_i$27 [1] \rdpick_INT_rb_o [3]
+    assign \fus_cu_rd__go_i$34 2'00
+    assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [3]
+    assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rb_o [3]
     sync init
   end
   process $group_149
-    assign \src1_i$28 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$28 \int_src1__data_o
+    assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$35 \int_src1__data_o
     sync init
   end
   process $group_150
-    assign \cu_rd__go_i$30 6'000000
-    assign \cu_rd__go_i$30 [0] \rdpick_INT_ra_o [4]
-    assign \cu_rd__go_i$30 [3] \rdpick_XER_xer_so_o [1]
-    assign \cu_rd__go_i$30 [5] \rdpick_XER_xer_ca_o [1]
-    assign \cu_rd__go_i$30 [4] \rdpick_XER_xer_ov_o
-    assign \cu_rd__go_i$30 [2] \rdpick_FAST_fast1_o [2]
-    assign \cu_rd__go_i$30 [1] \rdpick_SPR_spr1_o
+    assign \fus_cu_rd__go_i$37 6'000000
+    assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [4]
+    assign \fus_cu_rd__go_i$37 [3] \rdpick_XER_xer_so_o [1]
+    assign \fus_cu_rd__go_i$37 [5] \rdpick_XER_xer_ca_o [1]
+    assign \fus_cu_rd__go_i$37 [4] \rdpick_XER_xer_ov_o
+    assign \fus_cu_rd__go_i$37 [2] \rdpick_FAST_fast1_o [2]
+    assign \fus_cu_rd__go_i$37 [1] \rdpick_SPR_spr1_o
     sync init
   end
   process $group_151
-    assign \src1_i$31 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$31 \int_src1__data_o
+    assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$38 \int_src1__data_o
     sync init
   end
   process $group_152
-    assign \cu_rd__go_i$33 3'000
-    assign \cu_rd__go_i$33 [0] \rdpick_INT_ra_o [5]
-    assign \cu_rd__go_i$33 [1] \rdpick_INT_rb_o [4]
-    assign \cu_rd__go_i$33 [2] \rdpick_XER_xer_so_o [2]
+    assign \fus_cu_rd__go_i$40 3'000
+    assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [5]
+    assign \fus_cu_rd__go_i$40 [1] \rdpick_INT_rb_o [4]
+    assign \fus_cu_rd__go_i$40 [2] \rdpick_XER_xer_so_o [2]
     sync init
   end
   process $group_153
-    assign \src1_i$34 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$34 \int_src1__data_o
+    assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$41 \int_src1__data_o
     sync init
   end
   process $group_154
-    assign \cu_rd__go_i$36 4'0000
-    assign \cu_rd__go_i$36 [0] \rdpick_INT_ra_o [6]
-    assign \cu_rd__go_i$36 [1] \rdpick_INT_rb_o [5]
-    assign \cu_rd__go_i$36 [2] \rdpick_INT_rc_o [0]
-    assign \cu_rd__go_i$36 [3] \rdpick_XER_xer_ca_o [2]
+    assign \fus_cu_rd__go_i$43 4'0000
+    assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [6]
+    assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rb_o [5]
+    assign \fus_cu_rd__go_i$43 [2] \rdpick_INT_rc_o [0]
+    assign \fus_cu_rd__go_i$43 [3] \rdpick_XER_xer_ca_o [2]
     sync init
   end
   process $group_155
-    assign \src1_i$37 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$37 \int_src1__data_o
+    assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$44 \int_src1__data_o
     sync init
   end
   process $group_156
-    assign \cu_rd__go_i$39 3'000
-    assign \cu_rd__go_i$39 [0] \rdpick_INT_ra_o [7]
-    assign \cu_rd__go_i$39 [1] \rdpick_INT_rb_o [6]
-    assign \cu_rd__go_i$39 [2] \rdpick_INT_rc_o [1]
+    assign \fus_cu_rd__go_i$46 3'000
+    assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [7]
+    assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rb_o [6]
+    assign \fus_cu_rd__go_i$46 [2] \rdpick_INT_rc_o [1]
     sync init
   end
   process $group_157
-    assign \src1_i$40 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$40 \int_src1__data_o
+    assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$47 \int_src1__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_INT_rb
   process $group_158
     assign \rdflag_INT_rb 1'0
-    assign \rdflag_INT_rb \reg2_ok
+    assign \rdflag_INT_rb \pdecode2_reg2_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  wire width 32 $308
+  wire width 32 $273
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
-  cell $sshl $309
+  cell $sshl $274
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \reg2
-    connect \Y $308
+    connect \B \pdecode2_reg2
+    connect \Y $273
   end
   process $group_159
     assign \int_src2__ren 32'00000000000000000000000000000000
@@ -154067,257 +153605,257 @@ module \core
     switch { \rdpick_INT_rb_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src2__ren $308
+        assign \int_src2__ren $273
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $310
+  wire width 1 $275
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $311
+  cell $and $276
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [1]
+    connect \A \fus_cu_rd__rel_o [1]
     connect \B \fu_enable [0]
-    connect \Y $310
+    connect \Y $275
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $312
+  wire width 1 $277
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $313
+  cell $and $278
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $310
+    connect \A $275
     connect \B \rdflag_INT_rb
-    connect \Y $312
+    connect \Y $277
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $314
+  wire width 1 $279
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $315
+  cell $and $280
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [1]
+    connect \A \fus_cu_rd__rel_o$27 [1]
     connect \B \fu_enable [1]
-    connect \Y $314
+    connect \Y $279
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $316
+  wire width 1 $281
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $317
+  cell $and $282
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $314
+    connect \A $279
     connect \B \rdflag_INT_rb
-    connect \Y $316
+    connect \Y $281
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $318
+  wire width 1 $283
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $319
+  cell $and $284
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$23 [1]
+    connect \A \fus_cu_rd__rel_o$30 [1]
     connect \B \fu_enable [3]
-    connect \Y $318
+    connect \Y $283
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $320
+  wire width 1 $285
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $321
+  cell $and $286
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $318
+    connect \A $283
     connect \B \rdflag_INT_rb
-    connect \Y $320
+    connect \Y $285
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $322
+  wire width 1 $287
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $323
+  cell $and $288
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$26 [1]
+    connect \A \fus_cu_rd__rel_o$33 [1]
     connect \B \fu_enable [4]
-    connect \Y $322
+    connect \Y $287
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $324
+  wire width 1 $289
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $325
+  cell $and $290
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $322
+    connect \A $287
     connect \B \rdflag_INT_rb
-    connect \Y $324
+    connect \Y $289
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $326
+  wire width 1 $291
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $327
+  cell $and $292
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$32 [1]
+    connect \A \fus_cu_rd__rel_o$39 [1]
     connect \B \fu_enable [6]
-    connect \Y $326
+    connect \Y $291
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $328
+  wire width 1 $293
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $329
+  cell $and $294
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $326
+    connect \A $291
     connect \B \rdflag_INT_rb
-    connect \Y $328
+    connect \Y $293
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $330
+  wire width 1 $295
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $331
+  cell $and $296
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$35 [1]
+    connect \A \fus_cu_rd__rel_o$42 [1]
     connect \B \fu_enable [7]
-    connect \Y $330
+    connect \Y $295
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $332
+  wire width 1 $297
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $333
+  cell $and $298
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $330
+    connect \A $295
     connect \B \rdflag_INT_rb
-    connect \Y $332
+    connect \Y $297
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $334
+  wire width 1 $299
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $335
+  cell $and $300
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$38 [1]
+    connect \A \fus_cu_rd__rel_o$45 [1]
     connect \B \fu_enable [8]
-    connect \Y $334
+    connect \Y $299
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $336
+  wire width 1 $301
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $337
+  cell $and $302
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $334
+    connect \A $299
     connect \B \rdflag_INT_rb
-    connect \Y $336
+    connect \Y $301
   end
   process $group_160
     assign \rdpick_INT_rb_i 7'0000000
-    assign \rdpick_INT_rb_i [0] $312
-    assign \rdpick_INT_rb_i [1] $316
-    assign \rdpick_INT_rb_i [2] $320
-    assign \rdpick_INT_rb_i [3] $324
-    assign \rdpick_INT_rb_i [4] $328
-    assign \rdpick_INT_rb_i [5] $332
-    assign \rdpick_INT_rb_i [6] $336
+    assign \rdpick_INT_rb_i [0] $277
+    assign \rdpick_INT_rb_i [1] $281
+    assign \rdpick_INT_rb_i [2] $285
+    assign \rdpick_INT_rb_i [3] $289
+    assign \rdpick_INT_rb_i [4] $293
+    assign \rdpick_INT_rb_i [5] $297
+    assign \rdpick_INT_rb_i [6] $301
     sync init
   end
   process $group_161
-    assign \src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i \int_src2__data_o
+    assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i \int_src2__data_o
     sync init
   end
   process $group_162
-    assign \src2_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$41 \int_src2__data_o
+    assign \fus_src2_i$48 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$48 \int_src2__data_o
     sync init
   end
   process $group_163
-    assign \src2_i$42 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$42 \int_src2__data_o
+    assign \fus_src2_i$49 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$49 \int_src2__data_o
     sync init
   end
   process $group_164
-    assign \src2_i$43 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$43 \int_src2__data_o
+    assign \fus_src2_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$50 \int_src2__data_o
     sync init
   end
   process $group_165
-    assign \src2_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$44 \int_src2__data_o
+    assign \fus_src2_i$51 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$51 \int_src2__data_o
     sync init
   end
   process $group_166
-    assign \src2_i$45 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$45 \int_src2__data_o
+    assign \fus_src2_i$52 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$52 \int_src2__data_o
     sync init
   end
   process $group_167
-    assign \src2_i$46 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$46 \int_src2__data_o
+    assign \fus_src2_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$53 \int_src2__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_INT_rc
   process $group_168
     assign \rdflag_INT_rc 1'0
-    assign \rdflag_INT_rc \reg3_ok
+    assign \rdflag_INT_rc \pdecode2_reg3_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  wire width 32 $338
+  wire width 32 $303
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
-  cell $sshl $339
+  cell $sshl $304
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \reg3
-    connect \Y $338
+    connect \B \pdecode2_reg3
+    connect \Y $303
   end
   process $group_169
     assign \int_src3__ren 32'00000000000000000000000000000000
@@ -154325,66 +153863,66 @@ module \core
     switch { \rdpick_INT_rc_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \int_src3__ren $338
+        assign \int_src3__ren $303
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $340
+  wire width 1 $305
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $341
+  cell $and $306
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$35 [2]
+    connect \A \fus_cu_rd__rel_o$42 [2]
     connect \B \fu_enable [7]
-    connect \Y $340
+    connect \Y $305
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $342
+  wire width 1 $307
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $343
+  cell $and $308
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $340
+    connect \A $305
     connect \B \rdflag_INT_rc
-    connect \Y $342
+    connect \Y $307
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $344
+  wire width 1 $309
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $345
+  cell $and $310
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$38 [2]
+    connect \A \fus_cu_rd__rel_o$45 [2]
     connect \B \fu_enable [8]
-    connect \Y $344
+    connect \Y $309
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $346
+  wire width 1 $311
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $347
+  cell $and $312
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $344
+    connect \A $309
     connect \B \rdflag_INT_rc
-    connect \Y $346
+    connect \Y $311
   end
   process $group_170
     assign \rdpick_INT_rc_i 2'00
-    assign \rdpick_INT_rc_i [0] $342
-    assign \rdpick_INT_rc_i [1] $346
+    assign \rdpick_INT_rc_i [0] $307
+    assign \rdpick_INT_rc_i [1] $311
     sync init
   end
   process $group_171
@@ -154393,41 +153931,41 @@ module \core
     sync init
   end
   process $group_172
-    assign \src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src3_i \int_src3__data_o
+    assign \fus_src3_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$54 \int_src3__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $348
+  wire width 1 $313
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $349
+  cell $and $314
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $348
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $313
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $350
+  wire width 1 $315
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $351
+  cell $or $316
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $348
-    connect \B \xer_in
-    connect \Y $350
+    connect \A $313
+    connect \B \pdecode2_xer_in
+    connect \Y $315
   end
   process $group_173
     assign \rdflag_XER_xer_so 1'0
-    assign \rdflag_XER_xer_so $350
+    assign \rdflag_XER_xer_so $315
     sync init
   end
   process $group_174
@@ -154441,93 +153979,93 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $352
+  wire width 1 $317
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $353
+  cell $and $318
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [2]
+    connect \A \fus_cu_rd__rel_o [2]
     connect \B \fu_enable [0]
-    connect \Y $352
+    connect \Y $317
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $354
+  wire width 1 $319
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $355
+  cell $and $320
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $352
+    connect \A $317
     connect \B \rdflag_XER_xer_so
-    connect \Y $354
+    connect \Y $319
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $356
+  wire width 1 $321
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $357
+  cell $and $322
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [3]
+    connect \A \fus_cu_rd__rel_o$36 [3]
     connect \B \fu_enable [5]
-    connect \Y $356
+    connect \Y $321
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $358
+  wire width 1 $323
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $359
+  cell $and $324
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $356
+    connect \A $321
     connect \B \rdflag_XER_xer_so
-    connect \Y $358
+    connect \Y $323
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $360
+  wire width 1 $325
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $361
+  cell $and $326
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$32 [2]
+    connect \A \fus_cu_rd__rel_o$39 [2]
     connect \B \fu_enable [6]
-    connect \Y $360
+    connect \Y $325
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $362
+  wire width 1 $327
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $363
+  cell $and $328
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $360
+    connect \A $325
     connect \B \rdflag_XER_xer_so
-    connect \Y $362
+    connect \Y $327
   end
   process $group_175
     assign \rdpick_XER_xer_so_i 3'000
-    assign \rdpick_XER_xer_so_i [0] $354
-    assign \rdpick_XER_xer_so_i [1] $358
-    assign \rdpick_XER_xer_so_i [2] $362
+    assign \rdpick_XER_xer_so_i [0] $319
+    assign \rdpick_XER_xer_so_i [1] $323
+    assign \rdpick_XER_xer_so_i [2] $327
     sync init
   end
   process $group_176
-    assign \fus_src3_i$118 1'0
-    assign \fus_src3_i$118 \xer_src1__data_o [0]
+    assign \fus_src3_i$55 1'0
+    assign \fus_src3_i$55 \xer_src1__data_o [0]
     sync init
   end
   process $group_177
@@ -154536,41 +154074,41 @@ module \core
     sync init
   end
   process $group_178
-    assign \fus_src3_i$119 1'0
-    assign \fus_src3_i$119 \xer_src1__data_o [0]
+    assign \fus_src3_i$56 1'0
+    assign \fus_src3_i$56 \xer_src1__data_o [0]
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_ca
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $364
+  wire width 1 $329
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $365
+  cell $eq $330
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \input_carry
+    connect \A \pdecode2_input_carry
     connect \B 2'10
-    connect \Y $364
+    connect \Y $329
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $366
+  wire width 1 $331
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $367
+  cell $or $332
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $364
-    connect \B \xer_in
-    connect \Y $366
+    connect \A $329
+    connect \B \pdecode2_xer_in
+    connect \Y $331
   end
   process $group_179
     assign \rdflag_XER_xer_ca 1'0
-    assign \rdflag_XER_xer_ca $366
+    assign \rdflag_XER_xer_ca $331
     sync init
   end
   process $group_180
@@ -154584,93 +154122,93 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $368
+  wire width 1 $333
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $369
+  cell $and $334
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [3]
+    connect \A \fus_cu_rd__rel_o [3]
     connect \B \fu_enable [0]
-    connect \Y $368
+    connect \Y $333
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $370
+  wire width 1 $335
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $371
+  cell $and $336
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $368
+    connect \A $333
     connect \B \rdflag_XER_xer_ca
-    connect \Y $370
+    connect \Y $335
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $372
+  wire width 1 $337
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $373
+  cell $and $338
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [5]
+    connect \A \fus_cu_rd__rel_o$36 [5]
     connect \B \fu_enable [5]
-    connect \Y $372
+    connect \Y $337
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $374
+  wire width 1 $339
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $375
+  cell $and $340
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $372
+    connect \A $337
     connect \B \rdflag_XER_xer_ca
-    connect \Y $374
+    connect \Y $339
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $376
+  wire width 1 $341
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $377
+  cell $and $342
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$35 [3]
+    connect \A \fus_cu_rd__rel_o$42 [3]
     connect \B \fu_enable [7]
-    connect \Y $376
+    connect \Y $341
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $378
+  wire width 1 $343
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $379
+  cell $and $344
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $376
+    connect \A $341
     connect \B \rdflag_XER_xer_ca
-    connect \Y $378
+    connect \Y $343
   end
   process $group_181
     assign \rdpick_XER_xer_ca_i 3'000
-    assign \rdpick_XER_xer_ca_i [0] $370
-    assign \rdpick_XER_xer_ca_i [1] $374
-    assign \rdpick_XER_xer_ca_i [2] $378
+    assign \rdpick_XER_xer_ca_i [0] $335
+    assign \rdpick_XER_xer_ca_i [1] $339
+    assign \rdpick_XER_xer_ca_i [2] $343
     sync init
   end
   process $group_182
-    assign \fus_src4_i$120 2'00
-    assign \fus_src4_i$120 \xer_src2__data_o
+    assign \fus_src4_i$57 2'00
+    assign \fus_src4_i$57 \xer_src2__data_o
     sync init
   end
   process $group_183
@@ -154679,41 +154217,41 @@ module \core
     sync init
   end
   process $group_184
-    assign \fus_src4_i$121 2'00
-    assign \fus_src4_i$121 \xer_src2__data_o
+    assign \fus_src4_i$58 2'00
+    assign \fus_src4_i$58 \xer_src2__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_XER_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $380
+  wire width 1 $345
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $381
+  cell $and $346
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \oe
-    connect \B \oe_ok
-    connect \Y $380
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $345
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $382
+  wire width 1 $347
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $383
+  cell $or $348
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $380
-    connect \B \xer_in
-    connect \Y $382
+    connect \A $345
+    connect \B \pdecode2_xer_in
+    connect \Y $347
   end
   process $group_185
     assign \rdflag_XER_xer_ov 1'0
-    assign \rdflag_XER_xer_ov $382
+    assign \rdflag_XER_xer_ov $347
     sync init
   end
   process $group_186
@@ -154727,34 +154265,34 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $384
+  wire width 1 $349
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $385
+  cell $and $350
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [4]
+    connect \A \fus_cu_rd__rel_o$36 [4]
     connect \B \fu_enable [5]
-    connect \Y $384
+    connect \Y $349
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $386
+  wire width 1 $351
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $387
+  cell $and $352
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $384
+    connect \A $349
     connect \B \rdflag_XER_xer_ov
-    connect \Y $386
+    connect \Y $351
   end
   process $group_187
     assign \rdpick_XER_xer_ov_i 1'0
-    assign \rdpick_XER_xer_ov_i $386
+    assign \rdpick_XER_xer_ov_i $351
     sync init
   end
   process $group_188
@@ -154766,7 +154304,7 @@ module \core
   wire width 1 \rdflag_CR_full_cr
   process $group_189
     assign \rdflag_CR_full_cr 1'0
-    assign \rdflag_CR_full_cr \read_cr_whole
+    assign \rdflag_CR_full_cr \pdecode2_read_cr_whole
     sync init
   end
   process $group_190
@@ -154780,345 +154318,345 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $388
+  wire width 1 $353
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $389
+  cell $and $354
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [2]
+    connect \A \fus_cu_rd__rel_o$27 [2]
     connect \B \fu_enable [1]
-    connect \Y $388
+    connect \Y $353
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $390
+  wire width 1 $355
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $391
+  cell $and $356
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $388
+    connect \A $353
     connect \B \rdflag_CR_full_cr
-    connect \Y $390
+    connect \Y $355
   end
   process $group_191
     assign \rdpick_CR_full_cr_i 1'0
-    assign \rdpick_CR_full_cr_i $390
+    assign \rdpick_CR_full_cr_i $355
     sync init
   end
   process $group_192
-    assign \fus_src3_i$122 32'00000000000000000000000000000000
-    assign \fus_src3_i$122 \cr_full_rd__data_o
+    assign \fus_src3_i$59 32'00000000000000000000000000000000
+    assign \fus_src3_i$59 \cr_full_rd__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_a
   process $group_193
     assign \rdflag_CR_cr_a 1'0
-    assign \rdflag_CR_cr_a \cr_in1_ok
+    assign \rdflag_CR_cr_a \pdecode2_cr_in1_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $392
+  wire width 16 $357
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 4 $393
+  wire width 4 $358
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sub $394
+  cell $sub $359
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \cr_in1
-    connect \Y $393
+    connect \B \pdecode2_cr_in1
+    connect \Y $358
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $395
+  wire width 16 $360
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sshl $396
+  cell $sshl $361
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $393
-    connect \Y $395
+    connect \B $358
+    connect \Y $360
   end
-  connect $392 $395
+  connect $357 $360
   process $group_194
     assign \cr_src1__ren 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_a_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src1__ren $392 [7:0]
+        assign \cr_src1__ren $357 [7:0]
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $397
+  wire width 1 $362
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $398
+  cell $and $363
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [3]
+    connect \A \fus_cu_rd__rel_o$27 [3]
     connect \B \fu_enable [1]
-    connect \Y $397
+    connect \Y $362
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $399
+  wire width 1 $364
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $400
+  cell $and $365
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $397
+    connect \A $362
     connect \B \rdflag_CR_cr_a
-    connect \Y $399
+    connect \Y $364
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $401
+  wire width 1 $366
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $402
+  cell $and $367
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$47 [2]
+    connect \A \fus_cu_rd__rel_o$61 [2]
     connect \B \fu_enable [2]
-    connect \Y $401
+    connect \Y $366
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $403
+  wire width 1 $368
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $404
+  cell $and $369
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $401
+    connect \A $366
     connect \B \rdflag_CR_cr_a
-    connect \Y $403
+    connect \Y $368
   end
   process $group_195
     assign \rdpick_CR_cr_a_i 2'00
-    assign \rdpick_CR_cr_a_i [0] $399
-    assign \rdpick_CR_cr_a_i [1] $403
+    assign \rdpick_CR_cr_a_i [0] $364
+    assign \rdpick_CR_cr_a_i [1] $368
     sync init
   end
   process $group_196
-    assign \fus_src4_i$123 4'0000
-    assign \fus_src4_i$123 \cr_src1__data_o
+    assign \fus_src4_i$60 4'0000
+    assign \fus_src4_i$60 \cr_src1__data_o
     sync init
   end
   process $group_197
-    assign \cu_rd__go_i$48 3'000
-    assign \cu_rd__go_i$48 [2] \rdpick_CR_cr_a_o [1]
-    assign \cu_rd__go_i$48 [0] \rdpick_FAST_fast1_o [0]
-    assign \cu_rd__go_i$48 [1] \rdpick_FAST_fast2_o [0]
+    assign \fus_cu_rd__go_i$62 3'000
+    assign \fus_cu_rd__go_i$62 [2] \rdpick_CR_cr_a_o [1]
+    assign \fus_cu_rd__go_i$62 [0] \rdpick_FAST_fast1_o [0]
+    assign \fus_cu_rd__go_i$62 [1] \rdpick_FAST_fast2_o [0]
     sync init
   end
   process $group_198
-    assign \fus_src3_i$124 4'0000
-    assign \fus_src3_i$124 \cr_src1__data_o
+    assign \fus_src3_i$63 4'0000
+    assign \fus_src3_i$63 \cr_src1__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_b
   process $group_199
     assign \rdflag_CR_cr_b 1'0
-    assign \rdflag_CR_cr_b \cr_in2_ok
+    assign \rdflag_CR_cr_b \pdecode2_cr_in2_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $405
+  wire width 16 $370
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 4 $406
+  wire width 4 $371
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sub $407
+  cell $sub $372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \cr_in2
-    connect \Y $406
+    connect \B \pdecode2_cr_in2
+    connect \Y $371
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $408
+  wire width 16 $373
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sshl $409
+  cell $sshl $374
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $406
-    connect \Y $408
+    connect \B $371
+    connect \Y $373
   end
-  connect $405 $408
+  connect $370 $373
   process $group_200
     assign \cr_src2__ren 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_b_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src2__ren $405 [7:0]
+        assign \cr_src2__ren $370 [7:0]
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $410
+  wire width 1 $375
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $411
+  cell $and $376
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [4]
+    connect \A \fus_cu_rd__rel_o$27 [4]
     connect \B \fu_enable [1]
-    connect \Y $410
+    connect \Y $375
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $412
+  wire width 1 $377
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $413
+  cell $and $378
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $410
+    connect \A $375
     connect \B \rdflag_CR_cr_b
-    connect \Y $412
+    connect \Y $377
   end
   process $group_201
     assign \rdpick_CR_cr_b_i 1'0
-    assign \rdpick_CR_cr_b_i $412
+    assign \rdpick_CR_cr_b_i $377
     sync init
   end
   process $group_202
-    assign \fus_src5_i$125 4'0000
-    assign \fus_src5_i$125 \cr_src2__data_o
+    assign \fus_src5_i$64 4'0000
+    assign \fus_src5_i$64 \cr_src2__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_CR_cr_c
   process $group_203
     assign \rdflag_CR_cr_c 1'0
-    assign \rdflag_CR_cr_c \cr_in2_ok$3
+    assign \rdflag_CR_cr_c \pdecode2_cr_in2_ok$1
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $414
+  wire width 16 $379
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 4 $415
+  wire width 4 $380
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sub $416
+  cell $sub $381
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \cr_in2$49
-    connect \Y $415
+    connect \B \pdecode2_cr_in2$2
+    connect \Y $380
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $417
+  wire width 16 $382
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sshl $418
+  cell $sshl $383
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $415
-    connect \Y $417
+    connect \B $380
+    connect \Y $382
   end
-  connect $414 $417
+  connect $379 $382
   process $group_204
     assign \cr_src3__ren 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
     switch { \rdpick_CR_cr_c_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \cr_src3__ren $414 [7:0]
+        assign \cr_src3__ren $379 [7:0]
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $419
+  wire width 1 $384
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $420
+  cell $and $385
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$20 [5]
+    connect \A \fus_cu_rd__rel_o$27 [5]
     connect \B \fu_enable [1]
-    connect \Y $419
+    connect \Y $384
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $421
+  wire width 1 $386
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $422
+  cell $and $387
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $419
+    connect \A $384
     connect \B \rdflag_CR_cr_c
-    connect \Y $421
+    connect \Y $386
   end
   process $group_205
     assign \rdpick_CR_cr_c_i 1'0
-    assign \rdpick_CR_cr_c_i $421
+    assign \rdpick_CR_cr_c_i $386
     sync init
   end
   process $group_206
-    assign \fus_src6_i$126 4'0000
-    assign \fus_src6_i$126 \cr_src3__data_o
+    assign \fus_src6_i$65 4'0000
+    assign \fus_src6_i$65 \cr_src3__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_FAST_fast1
   process $group_207
     assign \rdflag_FAST_fast1 1'0
-    assign \rdflag_FAST_fast1 \fast1_ok
+    assign \rdflag_FAST_fast1 \pdecode2_fast1_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  wire width 8 $423
+  wire width 8 $388
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  cell $sshl $424
+  cell $sshl $389
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 8
     connect \A 1'1
-    connect \B \fast1
-    connect \Y $423
+    connect \B \pdecode2_fast1
+    connect \Y $388
   end
   process $group_208
     assign \fast_src1__ren 8'00000000
@@ -155126,129 +154664,129 @@ module \core
     switch { \rdpick_FAST_fast1_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \fast_src1__ren $423
+        assign \fast_src1__ren $388
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $425
+  wire width 1 $390
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $426
+  cell $and $391
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$47 [0]
+    connect \A \fus_cu_rd__rel_o$61 [0]
     connect \B \fu_enable [2]
-    connect \Y $425
+    connect \Y $390
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $427
+  wire width 1 $392
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $428
+  cell $and $393
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $425
+    connect \A $390
     connect \B \rdflag_FAST_fast1
-    connect \Y $427
+    connect \Y $392
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $429
+  wire width 1 $394
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $430
+  cell $and $395
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$23 [2]
+    connect \A \fus_cu_rd__rel_o$30 [2]
     connect \B \fu_enable [3]
-    connect \Y $429
+    connect \Y $394
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $431
+  wire width 1 $396
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $432
+  cell $and $397
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $429
+    connect \A $394
     connect \B \rdflag_FAST_fast1
-    connect \Y $431
+    connect \Y $396
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $433
+  wire width 1 $398
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $434
+  cell $and $399
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [2]
+    connect \A \fus_cu_rd__rel_o$36 [2]
     connect \B \fu_enable [5]
-    connect \Y $433
+    connect \Y $398
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $435
+  wire width 1 $400
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $436
+  cell $and $401
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $433
+    connect \A $398
     connect \B \rdflag_FAST_fast1
-    connect \Y $435
+    connect \Y $400
   end
   process $group_209
     assign \rdpick_FAST_fast1_i 3'000
-    assign \rdpick_FAST_fast1_i [0] $427
-    assign \rdpick_FAST_fast1_i [1] $431
-    assign \rdpick_FAST_fast1_i [2] $435
+    assign \rdpick_FAST_fast1_i [0] $392
+    assign \rdpick_FAST_fast1_i [1] $396
+    assign \rdpick_FAST_fast1_i [2] $400
     sync init
   end
   process $group_210
-    assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_i$50 \fast_src1__data_o
+    assign \fus_src1_i$66 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$66 \fast_src1__data_o
     sync init
   end
   process $group_211
-    assign \fus_src3_i$127 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$127 \fast_src1__data_o
+    assign \fus_src3_i$67 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$67 \fast_src1__data_o
     sync init
   end
   process $group_212
-    assign \fus_src3_i$128 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$128 \fast_src1__data_o
+    assign \fus_src3_i$68 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$68 \fast_src1__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_FAST_fast2
   process $group_213
     assign \rdflag_FAST_fast2 1'0
-    assign \rdflag_FAST_fast2 \fast2_ok
+    assign \rdflag_FAST_fast2 \pdecode2_fast2_ok
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  wire width 8 $437
+  wire width 8 $402
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  cell $sshl $438
+  cell $sshl $403
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 8
     connect \A 1'1
-    connect \B \fast2
-    connect \Y $437
+    connect \B \pdecode2_fast2
+    connect \Y $402
   end
   process $group_214
     assign \fast_src2__ren 8'00000000
@@ -155256,83 +154794,83 @@ module \core
     switch { \rdpick_FAST_fast2_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \fast_src2__ren $437
+        assign \fast_src2__ren $402
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $439
+  wire width 1 $404
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $440
+  cell $and $405
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$47 [1]
+    connect \A \fus_cu_rd__rel_o$61 [1]
     connect \B \fu_enable [2]
-    connect \Y $439
+    connect \Y $404
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $441
+  wire width 1 $406
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $442
+  cell $and $407
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $439
+    connect \A $404
     connect \B \rdflag_FAST_fast2
-    connect \Y $441
+    connect \Y $406
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $443
+  wire width 1 $408
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $444
+  cell $and $409
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$23 [3]
+    connect \A \fus_cu_rd__rel_o$30 [3]
     connect \B \fu_enable [3]
-    connect \Y $443
+    connect \Y $408
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $445
+  wire width 1 $410
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $446
+  cell $and $411
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $443
+    connect \A $408
     connect \B \rdflag_FAST_fast2
-    connect \Y $445
+    connect \Y $410
   end
   process $group_215
     assign \rdpick_FAST_fast2_i 2'00
-    assign \rdpick_FAST_fast2_i [0] $441
-    assign \rdpick_FAST_fast2_i [1] $445
+    assign \rdpick_FAST_fast2_i [0] $406
+    assign \rdpick_FAST_fast2_i [1] $410
     sync init
   end
   process $group_216
-    assign \src2_i$51 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$51 \fast_src2__data_o
+    assign \fus_src2_i$69 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$69 \fast_src2__data_o
     sync init
   end
   process $group_217
-    assign \fus_src4_i$129 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src4_i$129 \fast_src2__data_o
+    assign \fus_src4_i$70 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src4_i$70 \fast_src2__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
   wire width 1 \rdflag_SPR_spr1
   process $group_218
     assign \rdflag_SPR_spr1 1'0
-    assign \rdflag_SPR_spr1 \spr1_ok
+    assign \rdflag_SPR_spr1 \pdecode2_spr1_ok
     sync init
   end
   process $group_219
@@ -155341,58 +154879,58 @@ module \core
     switch { \rdpick_SPR_spr1_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
       case 1'1
-        assign \spr_src__ren \spr1 [0]
+        assign \spr_src__ren \pdecode2_spr1 [0]
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $447
+  wire width 1 $412
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $448
+  cell $and $413
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o$29 [1]
+    connect \A \fus_cu_rd__rel_o$36 [1]
     connect \B \fu_enable [5]
-    connect \Y $447
+    connect \Y $412
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $449
+  wire width 1 $414
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $450
+  cell $and $415
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $447
+    connect \A $412
     connect \B \rdflag_SPR_spr1
-    connect \Y $449
+    connect \Y $414
   end
   process $group_220
     assign \rdpick_SPR_spr1_i 1'0
-    assign \rdpick_SPR_spr1_i $449
+    assign \rdpick_SPR_spr1_i $414
     sync init
   end
   process $group_221
-    assign \src2_i$52 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_i$52 \spr_src__data_o
+    assign \fus_src2_i$71 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$71 \spr_src__data_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  wire width 32 $451
+  wire width 32 $416
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  cell $sshl $452
+  cell $sshl $417
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \rego
-    connect \Y $451
+    connect \B \pdecode2_rego
+    connect \Y $416
   end
   process $group_222
     assign \int_wen 32'00000000000000000000000000000000
@@ -155400,7 +154938,7 @@ module \core
     switch { \wrpick_INT_o_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \int_wen $451
+        assign \int_wen $416
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \int_wen 32'00000000000000000000000000000000
@@ -155410,143 +154948,143 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $453
+  wire width 1 $418
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $454
+  cell $and $419
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_o_ok
-    connect \B \cu_busy_o
-    connect \Y $453
+    connect \B \fus_cu_busy_o
+    connect \Y $418
   end
   process $group_223
     assign \wrflag_alu0_o_0 1'0
-    assign \wrflag_alu0_o_0 $453
+    assign \wrflag_alu0_o_0 $418
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $455
+  wire width 1 $420
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $456
+  cell $and $421
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o [0]
+    connect \A \fus_cu_wr__rel_o [0]
     connect \B \fu_enable [0]
-    connect \Y $455
+    connect \Y $420
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $457
+  wire width 1 $422
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $458
+  cell $and $423
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$53 [0]
+    connect \A \fus_cu_wr__rel_o$73 [0]
     connect \B \fu_enable [1]
-    connect \Y $457
+    connect \Y $422
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $459
+  wire width 1 $424
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $460
+  cell $and $425
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$55 [0]
+    connect \A \fus_cu_wr__rel_o$76 [0]
     connect \B \fu_enable [3]
-    connect \Y $459
+    connect \Y $424
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $461
+  wire width 1 $426
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $462
+  cell $and $427
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$57 [0]
+    connect \A \fus_cu_wr__rel_o$79 [0]
     connect \B \fu_enable [4]
-    connect \Y $461
+    connect \Y $426
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $463
+  wire width 1 $428
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $464
+  cell $and $429
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [0]
+    connect \A \fus_cu_wr__rel_o$82 [0]
     connect \B \fu_enable [5]
-    connect \Y $463
+    connect \Y $428
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $465
+  wire width 1 $430
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $466
+  cell $and $431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$61 [0]
+    connect \A \fus_cu_wr__rel_o$85 [0]
     connect \B \fu_enable [6]
-    connect \Y $465
+    connect \Y $430
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $467
+  wire width 1 $432
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $468
+  cell $and $433
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$63 [0]
+    connect \A \fus_cu_wr__rel_o$88 [0]
     connect \B \fu_enable [7]
-    connect \Y $467
+    connect \Y $432
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $469
+  wire width 1 $434
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $470
+  cell $and $435
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$65 [0]
+    connect \A \fus_cu_wr__rel_o$90 [0]
     connect \B \fu_enable [8]
-    connect \Y $469
+    connect \Y $434
   end
   process $group_224
     assign \wrpick_INT_o_i 8'00000000
-    assign \wrpick_INT_o_i [0] $455
-    assign \wrpick_INT_o_i [1] $457
-    assign \wrpick_INT_o_i [2] $459
-    assign \wrpick_INT_o_i [3] $461
-    assign \wrpick_INT_o_i [4] $463
-    assign \wrpick_INT_o_i [5] $465
-    assign \wrpick_INT_o_i [6] $467
-    assign \wrpick_INT_o_i [7] $469
+    assign \wrpick_INT_o_i [0] $420
+    assign \wrpick_INT_o_i [1] $422
+    assign \wrpick_INT_o_i [2] $424
+    assign \wrpick_INT_o_i [3] $426
+    assign \wrpick_INT_o_i [4] $428
+    assign \wrpick_INT_o_i [5] $430
+    assign \wrpick_INT_o_i [6] $432
+    assign \wrpick_INT_o_i [7] $434
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $471
+  wire width 1 $436
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $472
+  cell $and $437
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155554,12 +155092,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [0]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $471
+    connect \Y $436
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $473
+  wire width 1 $438
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $474
+  cell $and $439
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155567,12 +155105,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [0]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $473
+    connect \Y $438
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $475
+  wire width 1 $440
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $476
+  cell $and $441
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155580,12 +155118,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [0]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $475
+    connect \Y $440
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $477
+  wire width 1 $442
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $478
+  cell $and $443
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155593,12 +155131,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [0]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $477
+    connect \Y $442
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $479
+  wire width 1 $444
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $480
+  cell $and $445
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155606,41 +155144,41 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [0]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $479
+    connect \Y $444
   end
   process $group_225
-    assign \cu_wr__go_i 5'00000
-    assign \cu_wr__go_i [0] $471
-    assign \cu_wr__go_i [1] $473
-    assign \cu_wr__go_i [2] $475
-    assign \cu_wr__go_i [3] $477
-    assign \cu_wr__go_i [4] $479
+    assign \fus_cu_wr__go_i 5'00000
+    assign \fus_cu_wr__go_i [0] $436
+    assign \fus_cu_wr__go_i [1] $438
+    assign \fus_cu_wr__go_i [2] $440
+    assign \fus_cu_wr__go_i [3] $442
+    assign \fus_cu_wr__go_i [4] $444
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $481
+  wire width 1 $446
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $482
+  cell $and $447
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$130
-    connect \B \cu_busy_o$2
-    connect \Y $481
+    connect \A \fus_o_ok$72
+    connect \B \fus_cu_busy_o$4
+    connect \Y $446
   end
   process $group_226
     assign \wrflag_cr0_o_0 1'0
-    assign \wrflag_cr0_o_0 $481
+    assign \wrflag_cr0_o_0 $446
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $483
+  wire width 1 $448
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $484
+  cell $and $449
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155648,12 +155186,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [1]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $483
+    connect \Y $448
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $485
+  wire width 1 $450
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $486
+  cell $and $451
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155661,12 +155199,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_full_cr_o
     connect \B \wrpick_CR_full_cr_en_o
-    connect \Y $485
+    connect \Y $450
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $487
+  wire width 1 $452
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $488
+  cell $and $453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155674,39 +155212,39 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [1]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $487
+    connect \Y $452
   end
   process $group_227
-    assign \cu_wr__go_i$54 3'000
-    assign \cu_wr__go_i$54 [0] $483
-    assign \cu_wr__go_i$54 [1] $485
-    assign \cu_wr__go_i$54 [2] $487
+    assign \fus_cu_wr__go_i$74 3'000
+    assign \fus_cu_wr__go_i$74 [0] $448
+    assign \fus_cu_wr__go_i$74 [1] $450
+    assign \fus_cu_wr__go_i$74 [2] $452
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $489
+  wire width 1 $454
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $490
+  cell $and $455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$131
-    connect \B \cu_busy_o$9
-    connect \Y $489
+    connect \A \fus_o_ok$75
+    connect \B \fus_cu_busy_o$10
+    connect \Y $454
   end
   process $group_228
     assign \wrflag_trap0_o_0 1'0
-    assign \wrflag_trap0_o_0 $489
+    assign \wrflag_trap0_o_0 $454
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $491
+  wire width 1 $456
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $492
+  cell $and $457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155714,12 +155252,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [2]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $491
+    connect \Y $456
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $493
+  wire width 1 $458
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $494
+  cell $and $459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155727,12 +155265,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [1]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $493
+    connect \Y $458
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $495
+  wire width 1 $460
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $496
+  cell $and $461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155740,12 +155278,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast2_o [1]
     connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $495
+    connect \Y $460
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $497
+  wire width 1 $462
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $498
+  cell $and $463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155753,12 +155291,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_nia_o [1]
     connect \B \wrpick_FAST_nia_en_o
-    connect \Y $497
+    connect \Y $462
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $499
+  wire width 1 $464
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $500
+  cell $and $465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155766,41 +155304,41 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_msr_o
     connect \B \wrpick_FAST_msr_en_o
-    connect \Y $499
+    connect \Y $464
   end
   process $group_229
-    assign \cu_wr__go_i$56 5'00000
-    assign \cu_wr__go_i$56 [0] $491
-    assign \cu_wr__go_i$56 [1] $493
-    assign \cu_wr__go_i$56 [2] $495
-    assign \cu_wr__go_i$56 [3] $497
-    assign \cu_wr__go_i$56 [4] $499
+    assign \fus_cu_wr__go_i$77 5'00000
+    assign \fus_cu_wr__go_i$77 [0] $456
+    assign \fus_cu_wr__go_i$77 [1] $458
+    assign \fus_cu_wr__go_i$77 [2] $460
+    assign \fus_cu_wr__go_i$77 [3] $462
+    assign \fus_cu_wr__go_i$77 [4] $464
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $501
+  wire width 1 $466
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $502
+  cell $and $467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$132
-    connect \B \cu_busy_o$11
-    connect \Y $501
+    connect \A \fus_o_ok$78
+    connect \B \fus_cu_busy_o$13
+    connect \Y $466
   end
   process $group_230
     assign \wrflag_logical0_o_0 1'0
-    assign \wrflag_logical0_o_0 $501
+    assign \wrflag_logical0_o_0 $466
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $503
+  wire width 1 $468
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $504
+  cell $and $469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155808,12 +155346,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [3]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $503
+    connect \Y $468
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $505
+  wire width 1 $470
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $506
+  cell $and $471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155821,12 +155359,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [2]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $505
+    connect \Y $470
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $507
+  wire width 1 $472
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $508
+  cell $and $473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155834,39 +155372,39 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [1]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $507
+    connect \Y $472
   end
   process $group_231
-    assign \cu_wr__go_i$58 3'000
-    assign \cu_wr__go_i$58 [0] $503
-    assign \cu_wr__go_i$58 [1] $505
-    assign \cu_wr__go_i$58 [2] $507
+    assign \fus_cu_wr__go_i$80 3'000
+    assign \fus_cu_wr__go_i$80 [0] $468
+    assign \fus_cu_wr__go_i$80 [1] $470
+    assign \fus_cu_wr__go_i$80 [2] $472
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $509
+  wire width 1 $474
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $510
+  cell $and $475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$133
-    connect \B \cu_busy_o$13
-    connect \Y $509
+    connect \A \fus_o_ok$81
+    connect \B \fus_cu_busy_o$16
+    connect \Y $474
   end
   process $group_232
     assign \wrflag_spr0_o_0 1'0
-    assign \wrflag_spr0_o_0 $509
+    assign \wrflag_spr0_o_0 $474
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $511
+  wire width 1 $476
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $512
+  cell $and $477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155874,12 +155412,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [4]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $511
+    connect \Y $476
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $513
+  wire width 1 $478
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $514
+  cell $and $479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155887,12 +155425,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [2]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $513
+    connect \Y $478
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $515
+  wire width 1 $480
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $516
+  cell $and $481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155900,12 +155438,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [1]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $515
+    connect \Y $480
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $517
+  wire width 1 $482
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $518
+  cell $and $483
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155913,12 +155451,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [1]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $517
+    connect \Y $482
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $519
+  wire width 1 $484
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $520
+  cell $and $485
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155926,12 +155464,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [2]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $519
+    connect \Y $484
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $521
+  wire width 1 $486
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $522
+  cell $and $487
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155939,42 +155477,42 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_SPR_spr1_o
     connect \B \wrpick_SPR_spr1_en_o
-    connect \Y $521
+    connect \Y $486
   end
   process $group_233
-    assign \cu_wr__go_i$60 6'000000
-    assign \cu_wr__go_i$60 [0] $511
-    assign \cu_wr__go_i$60 [5] $513
-    assign \cu_wr__go_i$60 [4] $515
-    assign \cu_wr__go_i$60 [3] $517
-    assign \cu_wr__go_i$60 [2] $519
-    assign \cu_wr__go_i$60 [1] $521
+    assign \fus_cu_wr__go_i$83 6'000000
+    assign \fus_cu_wr__go_i$83 [0] $476
+    assign \fus_cu_wr__go_i$83 [5] $478
+    assign \fus_cu_wr__go_i$83 [4] $480
+    assign \fus_cu_wr__go_i$83 [3] $482
+    assign \fus_cu_wr__go_i$83 [2] $484
+    assign \fus_cu_wr__go_i$83 [1] $486
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $523
+  wire width 1 $488
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $524
+  cell $and $489
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$134
-    connect \B \cu_busy_o$15
-    connect \Y $523
+    connect \A \fus_o_ok$84
+    connect \B \fus_cu_busy_o$19
+    connect \Y $488
   end
   process $group_234
     assign \wrflag_mul0_o_0 1'0
-    assign \wrflag_mul0_o_0 $523
+    assign \wrflag_mul0_o_0 $488
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $525
+  wire width 1 $490
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $526
+  cell $and $491
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155982,12 +155520,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [5]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $525
+    connect \Y $490
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $527
+  wire width 1 $492
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $528
+  cell $and $493
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -155995,12 +155533,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [3]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $527
+    connect \Y $492
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $529
+  wire width 1 $494
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $530
+  cell $and $495
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156008,12 +155546,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ov_o [2]
     connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $529
+    connect \Y $494
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $531
+  wire width 1 $496
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $532
+  cell $and $497
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156021,40 +155559,40 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_so_o [2]
     connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $531
+    connect \Y $496
   end
   process $group_235
-    assign \cu_wr__go_i$62 4'0000
-    assign \cu_wr__go_i$62 [0] $525
-    assign \cu_wr__go_i$62 [1] $527
-    assign \cu_wr__go_i$62 [2] $529
-    assign \cu_wr__go_i$62 [3] $531
+    assign \fus_cu_wr__go_i$86 4'0000
+    assign \fus_cu_wr__go_i$86 [0] $490
+    assign \fus_cu_wr__go_i$86 [1] $492
+    assign \fus_cu_wr__go_i$86 [2] $494
+    assign \fus_cu_wr__go_i$86 [3] $496
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_o_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $533
+  wire width 1 $498
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $534
+  cell $and $499
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$135
-    connect \B \cu_busy_o$17
-    connect \Y $533
+    connect \A \fus_o_ok$87
+    connect \B \fus_cu_busy_o$22
+    connect \Y $498
   end
   process $group_236
     assign \wrflag_shiftrot0_o_0 1'0
-    assign \wrflag_shiftrot0_o_0 $533
+    assign \wrflag_shiftrot0_o_0 $498
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $535
+  wire width 1 $500
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $536
+  cell $and $501
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156062,12 +155600,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [6]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $535
+    connect \Y $500
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $537
+  wire width 1 $502
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $538
+  cell $and $503
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156075,12 +155613,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_CR_cr_a_o [4]
     connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $537
+    connect \Y $502
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $539
+  wire width 1 $504
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $540
+  cell $and $505
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156088,39 +155626,41 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_XER_xer_ca_o [3]
     connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $539
+    connect \Y $504
   end
   process $group_237
-    assign \cu_wr__go_i$64 3'000
-    assign \cu_wr__go_i$64 [0] $535
-    assign \cu_wr__go_i$64 [1] $537
-    assign \cu_wr__go_i$64 [2] $539
+    assign \fus_cu_wr__go_i$89 3'000
+    assign \fus_cu_wr__go_i$89 [0] $500
+    assign \fus_cu_wr__go_i$89 [1] $502
+    assign \fus_cu_wr__go_i$89 [2] $504
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_ldst0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $541
+  wire width 1 $506
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $542
+  cell $and $507
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \o_ok
-    connect \B \cu_busy_o$19
-    connect \Y $541
+    connect \B \fus_cu_busy_o$25
+    connect \Y $506
   end
   process $group_238
     assign \wrflag_ldst0_o_0 1'0
-    assign \wrflag_ldst0_o_0 $541
+    assign \wrflag_ldst0_o_0 $506
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $543
+  wire width 1 $508
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $544
+  cell $and $509
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156128,12 +155668,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o_o [7]
     connect \B \wrpick_INT_o_en_o
-    connect \Y $543
+    connect \Y $508
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $545
+  wire width 1 $510
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $546
+  cell $and $511
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -156141,180 +155681,182 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_INT_o1_o
     connect \B \wrpick_INT_o1_en_o
-    connect \Y $545
+    connect \Y $510
   end
   process $group_239
-    assign \cu_wr__go_i$66 2'00
-    assign \cu_wr__go_i$66 [0] $543
-    assign \cu_wr__go_i$66 [1] $545
+    assign \fus_cu_wr__go_i$91 2'00
+    assign \fus_cu_wr__go_i$91 [0] $508
+    assign \fus_cu_wr__go_i$91 [1] $510
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $547
+  wire width 65 $512
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $548
+  wire width 64 $513
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $549
+  cell $or $514
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o
-    connect \B \dest1_o$67
-    connect \Y $548
+    connect \A \fus_dest1_o
+    connect \B \fus_dest1_o$92
+    connect \Y $513
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $550
+  wire width 64 $515
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $551
+  cell $or $516
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$68
-    connect \B \dest1_o$69
-    connect \Y $550
+    connect \A \fus_dest1_o$93
+    connect \B \fus_dest1_o$94
+    connect \Y $515
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $552
+  wire width 64 $517
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $553
+  cell $or $518
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $548
-    connect \B $550
-    connect \Y $552
+    connect \A $513
+    connect \B $515
+    connect \Y $517
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $554
+  wire width 64 $519
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $555
+  cell $or $520
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$70
-    connect \B \dest1_o$71
-    connect \Y $554
+    connect \A \fus_dest1_o$95
+    connect \B \fus_dest1_o$96
+    connect \Y $519
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 65 $556
+  wire width 65 $521
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $557
+  cell $or $522
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A \dest1_o$72
-    connect \B { \o_ok \o }
-    connect \Y $556
+    connect \A \fus_dest1_o$97
+    connect \B { \o_ok \fus_o }
+    connect \Y $521
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $558
+  wire width 65 $523
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $559
+  cell $or $524
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A $554
-    connect \B $556
-    connect \Y $558
+    connect \A $519
+    connect \B $521
+    connect \Y $523
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $560
+  wire width 65 $525
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $561
+  cell $or $526
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 65
     parameter \Y_WIDTH 65
-    connect \A $552
-    connect \B $558
-    connect \Y $560
+    connect \A $517
+    connect \B $523
+    connect \Y $525
   end
-  connect $547 $560
+  connect $512 $525
   process $group_240
     assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i $547 [63:0]
+    assign \int_data_i $512 [63:0]
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  wire width 32 $562
+  wire width 32 $527
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  cell $sshl $563
+  cell $sshl $528
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \ea
-    connect \Y $562
+    connect \B \pdecode2_ea
+    connect \Y $527
   end
   process $group_241
-    assign \int_wen$170 32'00000000000000000000000000000000
+    assign \int_wen$135 32'00000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_INT_o1_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \int_wen$170 $562
+        assign \int_wen$135 $527
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \int_wen$170 32'00000000000000000000000000000000
+        assign \int_wen$135 32'00000000000000000000000000000000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_ldst0_o1_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \ea_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $564
+  wire width 1 $529
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $565
+  cell $and $530
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \ea_ok
-    connect \B \cu_busy_o$19
-    connect \Y $564
+    connect \B \fus_cu_busy_o$25
+    connect \Y $529
   end
   process $group_242
     assign \wrflag_ldst0_o1_1 1'0
-    assign \wrflag_ldst0_o1_1 $564
+    assign \wrflag_ldst0_o1_1 $529
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $566
+  wire width 1 $531
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $567
+  cell $and $532
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$65 [1]
+    connect \A \fus_cu_wr__rel_o$90 [1]
     connect \B \fu_enable [8]
-    connect \Y $566
+    connect \Y $531
   end
   process $group_243
     assign \wrpick_INT_o1_i 1'0
-    assign \wrpick_INT_o1_i $566
+    assign \wrpick_INT_o1_i $531
     sync init
   end
   process $group_244
-    assign \int_data_i$171 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i$171 { \ea_ok \ea$73 } [63:0]
+    assign \int_data_i$136 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \int_data_i$136 { \ea_ok \fus_ea } [63:0]
     sync init
   end
   process $group_245
@@ -156333,39 +155875,39 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_full_cr_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $568
+  wire width 1 $533
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $569
+  cell $and $534
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_full_cr_ok
-    connect \B \cu_busy_o$2
-    connect \Y $568
+    connect \B \fus_cu_busy_o$4
+    connect \Y $533
   end
   process $group_246
     assign \wrflag_cr0_full_cr_1 1'0
-    assign \wrflag_cr0_full_cr_1 $568
+    assign \wrflag_cr0_full_cr_1 $533
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $570
+  wire width 1 $535
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $571
+  cell $and $536
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$53 [1]
+    connect \A \fus_cu_wr__rel_o$73 [1]
     connect \B \fu_enable [1]
-    connect \Y $570
+    connect \Y $535
   end
   process $group_247
     assign \wrpick_CR_full_cr_i 1'0
-    assign \wrpick_CR_full_cr_i $570
+    assign \wrpick_CR_full_cr_i $535
     sync init
   end
   process $group_248
@@ -156374,41 +155916,41 @@ module \core
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $572
+  wire width 16 $537
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 4 $573
+  wire width 4 $538
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sub $574
+  cell $sub $539
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \cr_out
-    connect \Y $573
+    connect \B \pdecode2_cr_out
+    connect \Y $538
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $575
+  wire width 16 $540
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sshl $576
+  cell $sshl $541
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $573
-    connect \Y $575
+    connect \B $538
+    connect \Y $540
   end
-  connect $572 $575
+  connect $537 $540
   process $group_249
     assign \cr_wen 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_CR_cr_a_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \cr_wen $572 [7:0]
+        assign \cr_wen $537 [7:0]
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \cr_wen 8'00000000
@@ -156418,232 +155960,232 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_cr_a_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $577
+  wire width 1 $542
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $578
+  cell $and $543
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_cr_a_ok
-    connect \B \cu_busy_o
-    connect \Y $577
+    connect \B \fus_cu_busy_o
+    connect \Y $542
   end
   process $group_250
     assign \wrflag_alu0_cr_a_1 1'0
-    assign \wrflag_alu0_cr_a_1 $577
+    assign \wrflag_alu0_cr_a_1 $542
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $579
+  wire width 1 $544
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $580
+  cell $and $545
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o [1]
+    connect \A \fus_cu_wr__rel_o [1]
     connect \B \fu_enable [0]
-    connect \Y $579
+    connect \Y $544
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $581
+  wire width 1 $546
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $582
+  cell $and $547
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$53 [2]
+    connect \A \fus_cu_wr__rel_o$73 [2]
     connect \B \fu_enable [1]
-    connect \Y $581
+    connect \Y $546
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $583
+  wire width 1 $548
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $584
+  cell $and $549
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$57 [1]
+    connect \A \fus_cu_wr__rel_o$79 [1]
     connect \B \fu_enable [4]
-    connect \Y $583
+    connect \Y $548
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $585
+  wire width 1 $550
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $586
+  cell $and $551
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$61 [1]
+    connect \A \fus_cu_wr__rel_o$85 [1]
     connect \B \fu_enable [6]
-    connect \Y $585
+    connect \Y $550
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $587
+  wire width 1 $552
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $588
+  cell $and $553
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$63 [1]
+    connect \A \fus_cu_wr__rel_o$88 [1]
     connect \B \fu_enable [7]
-    connect \Y $587
+    connect \Y $552
   end
   process $group_251
     assign \wrpick_CR_cr_a_i 5'00000
-    assign \wrpick_CR_cr_a_i [0] $579
-    assign \wrpick_CR_cr_a_i [1] $581
-    assign \wrpick_CR_cr_a_i [2] $583
-    assign \wrpick_CR_cr_a_i [3] $585
-    assign \wrpick_CR_cr_a_i [4] $587
+    assign \wrpick_CR_cr_a_i [0] $544
+    assign \wrpick_CR_cr_a_i [1] $546
+    assign \wrpick_CR_cr_a_i [2] $548
+    assign \wrpick_CR_cr_a_i [3] $550
+    assign \wrpick_CR_cr_a_i [4] $552
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_cr0_cr_a_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $589
+  wire width 1 $554
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $590
+  cell $and $555
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$136
-    connect \B \cu_busy_o$2
-    connect \Y $589
+    connect \A \fus_cr_a_ok$98
+    connect \B \fus_cu_busy_o$4
+    connect \Y $554
   end
   process $group_252
     assign \wrflag_cr0_cr_a_2 1'0
-    assign \wrflag_cr0_cr_a_2 $589
+    assign \wrflag_cr0_cr_a_2 $554
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_cr_a_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $591
+  wire width 1 $556
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $592
+  cell $and $557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$137
-    connect \B \cu_busy_o$11
-    connect \Y $591
+    connect \A \fus_cr_a_ok$99
+    connect \B \fus_cu_busy_o$13
+    connect \Y $556
   end
   process $group_253
     assign \wrflag_logical0_cr_a_1 1'0
-    assign \wrflag_logical0_cr_a_1 $591
+    assign \wrflag_logical0_cr_a_1 $556
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_cr_a_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $593
+  wire width 1 $558
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $594
+  cell $and $559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$138
-    connect \B \cu_busy_o$15
-    connect \Y $593
+    connect \A \fus_cr_a_ok$100
+    connect \B \fus_cu_busy_o$19
+    connect \Y $558
   end
   process $group_254
     assign \wrflag_mul0_cr_a_1 1'0
-    assign \wrflag_mul0_cr_a_1 $593
+    assign \wrflag_mul0_cr_a_1 $558
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_cr_a_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $595
+  wire width 1 $560
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $596
+  cell $and $561
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$139
-    connect \B \cu_busy_o$17
-    connect \Y $595
+    connect \A \fus_cr_a_ok$101
+    connect \B \fus_cu_busy_o$22
+    connect \Y $560
   end
   process $group_255
     assign \wrflag_shiftrot0_cr_a_1 1'0
-    assign \wrflag_shiftrot0_cr_a_1 $595
+    assign \wrflag_shiftrot0_cr_a_1 $560
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $597
+  wire width 4 $562
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $598
+  cell $or $563
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$140
+    connect \A \fus_dest2_o$102
     connect \B \fus_dest3_o
-    connect \Y $597
+    connect \Y $562
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $599
+  wire width 4 $564
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $600
+  cell $or $565
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$142
-    connect \B \fus_dest2_o$143
-    connect \Y $599
+    connect \A \fus_dest2_o$104
+    connect \B \fus_dest2_o$105
+    connect \Y $564
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $601
+  wire width 4 $566
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $602
+  cell $or $567
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$141
-    connect \B $599
-    connect \Y $601
+    connect \A \fus_dest2_o$103
+    connect \B $564
+    connect \Y $566
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $603
+  wire width 4 $568
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $604
+  cell $or $569
     parameter \A_SIGNED 0
     parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 4
-    connect \A $597
-    connect \B $601
-    connect \Y $603
+    connect \A $562
+    connect \B $566
+    connect \Y $568
   end
   process $group_256
     assign \cr_data_i 4'0000
-    assign \cr_data_i $603
+    assign \cr_data_i $568
     sync init
   end
   process $group_257
@@ -156662,509 +156204,509 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_ca_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $605
+  wire width 1 $570
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $606
+  cell $and $571
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_ca_ok
-    connect \B \cu_busy_o
-    connect \Y $605
+    connect \B \fus_cu_busy_o
+    connect \Y $570
   end
   process $group_258
     assign \wrflag_alu0_xer_ca_2 1'0
-    assign \wrflag_alu0_xer_ca_2 $605
+    assign \wrflag_alu0_xer_ca_2 $570
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $607
+  wire width 1 $572
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $608
+  cell $and $573
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o [2]
+    connect \A \fus_cu_wr__rel_o [2]
     connect \B \fu_enable [0]
-    connect \Y $607
+    connect \Y $572
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $609
+  wire width 1 $574
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $610
+  cell $and $575
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$57 [2]
+    connect \A \fus_cu_wr__rel_o$79 [2]
     connect \B \fu_enable [4]
-    connect \Y $609
+    connect \Y $574
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $611
+  wire width 1 $576
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $612
+  cell $and $577
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [5]
+    connect \A \fus_cu_wr__rel_o$82 [5]
     connect \B \fu_enable [5]
-    connect \Y $611
+    connect \Y $576
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $613
+  wire width 1 $578
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $614
+  cell $and $579
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$63 [2]
+    connect \A \fus_cu_wr__rel_o$88 [2]
     connect \B \fu_enable [7]
-    connect \Y $613
+    connect \Y $578
   end
   process $group_259
     assign \wrpick_XER_xer_ca_i 4'0000
-    assign \wrpick_XER_xer_ca_i [0] $607
-    assign \wrpick_XER_xer_ca_i [1] $609
-    assign \wrpick_XER_xer_ca_i [2] $611
-    assign \wrpick_XER_xer_ca_i [3] $613
+    assign \wrpick_XER_xer_ca_i [0] $572
+    assign \wrpick_XER_xer_ca_i [1] $574
+    assign \wrpick_XER_xer_ca_i [2] $576
+    assign \wrpick_XER_xer_ca_i [3] $578
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_logical0_xer_ca_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $615
+  wire width 1 $580
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $616
+  cell $and $581
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$144
-    connect \B \cu_busy_o$11
-    connect \Y $615
+    connect \A \fus_xer_ca_ok$106
+    connect \B \fus_cu_busy_o$13
+    connect \Y $580
   end
   process $group_260
     assign \wrflag_logical0_xer_ca_2 1'0
-    assign \wrflag_logical0_xer_ca_2 $615
+    assign \wrflag_logical0_xer_ca_2 $580
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_ca_5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $617
+  wire width 1 $582
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $618
+  cell $and $583
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$145
-    connect \B \cu_busy_o$13
-    connect \Y $617
+    connect \A \fus_xer_ca_ok$107
+    connect \B \fus_cu_busy_o$16
+    connect \Y $582
   end
   process $group_261
     assign \wrflag_spr0_xer_ca_5 1'0
-    assign \wrflag_spr0_xer_ca_5 $617
+    assign \wrflag_spr0_xer_ca_5 $582
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_shiftrot0_xer_ca_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $619
+  wire width 1 $584
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $620
+  cell $and $585
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$146
-    connect \B \cu_busy_o$17
-    connect \Y $619
+    connect \A \fus_xer_ca_ok$108
+    connect \B \fus_cu_busy_o$22
+    connect \Y $584
   end
   process $group_262
     assign \wrflag_shiftrot0_xer_ca_2 1'0
-    assign \wrflag_shiftrot0_xer_ca_2 $619
+    assign \wrflag_shiftrot0_xer_ca_2 $584
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $621
+  wire width 2 $586
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $622
+  cell $or $587
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A \fus_dest3_o$147
-    connect \B \fus_dest3_o$148
-    connect \Y $621
+    connect \A \fus_dest3_o$109
+    connect \B \fus_dest3_o$110
+    connect \Y $586
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $623
+  wire width 2 $588
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $624
+  cell $or $589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest6_o
-    connect \B \fus_dest3_o$149
-    connect \Y $623
+    connect \B \fus_dest3_o$111
+    connect \Y $588
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $625
+  wire width 2 $590
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $626
+  cell $or $591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A $621
-    connect \B $623
-    connect \Y $625
+    connect \A $586
+    connect \B $588
+    connect \Y $590
   end
   process $group_263
     assign \xer_data_i 2'00
-    assign \xer_data_i $625
+    assign \xer_data_i $590
     sync init
   end
   process $group_264
-    assign \xer_wen$172 3'000
+    assign \xer_wen$137 3'000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_XER_xer_ov_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \xer_wen$172 3'100
+        assign \xer_wen$137 3'100
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \xer_wen$172 3'000
+        assign \xer_wen$137 3'000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_ov_3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $627
+  wire width 1 $592
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $628
+  cell $and $593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_ov_ok
-    connect \B \cu_busy_o
-    connect \Y $627
+    connect \B \fus_cu_busy_o
+    connect \Y $592
   end
   process $group_265
     assign \wrflag_alu0_xer_ov_3 1'0
-    assign \wrflag_alu0_xer_ov_3 $627
+    assign \wrflag_alu0_xer_ov_3 $592
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $629
+  wire width 1 $594
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $630
+  cell $and $595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o [3]
+    connect \A \fus_cu_wr__rel_o [3]
     connect \B \fu_enable [0]
-    connect \Y $629
+    connect \Y $594
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $631
+  wire width 1 $596
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $632
+  cell $and $597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [4]
+    connect \A \fus_cu_wr__rel_o$82 [4]
     connect \B \fu_enable [5]
-    connect \Y $631
+    connect \Y $596
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $633
+  wire width 1 $598
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $634
+  cell $and $599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$61 [2]
+    connect \A \fus_cu_wr__rel_o$85 [2]
     connect \B \fu_enable [6]
-    connect \Y $633
+    connect \Y $598
   end
   process $group_266
     assign \wrpick_XER_xer_ov_i 3'000
-    assign \wrpick_XER_xer_ov_i [0] $629
-    assign \wrpick_XER_xer_ov_i [1] $631
-    assign \wrpick_XER_xer_ov_i [2] $633
+    assign \wrpick_XER_xer_ov_i [0] $594
+    assign \wrpick_XER_xer_ov_i [1] $596
+    assign \wrpick_XER_xer_ov_i [2] $598
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_ov_4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $635
+  wire width 1 $600
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $636
+  cell $and $601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$150
-    connect \B \cu_busy_o$13
-    connect \Y $635
+    connect \A \fus_xer_ov_ok$112
+    connect \B \fus_cu_busy_o$16
+    connect \Y $600
   end
   process $group_267
     assign \wrflag_spr0_xer_ov_4 1'0
-    assign \wrflag_spr0_xer_ov_4 $635
+    assign \wrflag_spr0_xer_ov_4 $600
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_xer_ov_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $637
+  wire width 1 $602
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $638
+  cell $and $603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$151
-    connect \B \cu_busy_o$15
-    connect \Y $637
+    connect \A \fus_xer_ov_ok$113
+    connect \B \fus_cu_busy_o$19
+    connect \Y $602
   end
   process $group_268
     assign \wrflag_mul0_xer_ov_2 1'0
-    assign \wrflag_mul0_xer_ov_2 $637
+    assign \wrflag_mul0_xer_ov_2 $602
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $639
+  wire width 2 $604
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $640
+  cell $or $605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest5_o
-    connect \B \fus_dest3_o$152
-    connect \Y $639
+    connect \B \fus_dest3_o$114
+    connect \Y $604
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $641
+  wire width 2 $606
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $642
+  cell $or $607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
     connect \A \fus_dest4_o
-    connect \B $639
-    connect \Y $641
+    connect \B $604
+    connect \Y $606
   end
   process $group_269
-    assign \xer_data_i$173 2'00
-    assign \xer_data_i$173 $641
+    assign \xer_data_i$138 2'00
+    assign \xer_data_i$138 $606
     sync init
   end
   process $group_270
-    assign \xer_wen$174 3'000
+    assign \xer_wen$139 3'000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_XER_xer_so_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \xer_wen$174 3'001
+        assign \xer_wen$139 3'001
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \xer_wen$174 3'000
+        assign \xer_wen$139 3'000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_alu0_xer_so_4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $643
+  wire width 1 $608
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $644
+  cell $and $609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_xer_so_ok
-    connect \B \cu_busy_o
-    connect \Y $643
+    connect \B \fus_cu_busy_o
+    connect \Y $608
   end
   process $group_271
     assign \wrflag_alu0_xer_so_4 1'0
-    assign \wrflag_alu0_xer_so_4 $643
+    assign \wrflag_alu0_xer_so_4 $608
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $645
+  wire width 1 $610
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $646
+  cell $and $611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o [4]
+    connect \A \fus_cu_wr__rel_o [4]
     connect \B \fu_enable [0]
-    connect \Y $645
+    connect \Y $610
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $647
+  wire width 1 $612
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $648
+  cell $and $613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [3]
+    connect \A \fus_cu_wr__rel_o$82 [3]
     connect \B \fu_enable [5]
-    connect \Y $647
+    connect \Y $612
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $649
+  wire width 1 $614
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $650
+  cell $and $615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$61 [3]
+    connect \A \fus_cu_wr__rel_o$85 [3]
     connect \B \fu_enable [6]
-    connect \Y $649
+    connect \Y $614
   end
   process $group_272
     assign \wrpick_XER_xer_so_i 3'000
-    assign \wrpick_XER_xer_so_i [0] $645
-    assign \wrpick_XER_xer_so_i [1] $647
-    assign \wrpick_XER_xer_so_i [2] $649
+    assign \wrpick_XER_xer_so_i [0] $610
+    assign \wrpick_XER_xer_so_i [1] $612
+    assign \wrpick_XER_xer_so_i [2] $614
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_xer_so_3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $651
+  wire width 1 $616
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $652
+  cell $and $617
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$153
-    connect \B \cu_busy_o$13
-    connect \Y $651
+    connect \A \fus_xer_so_ok$115
+    connect \B \fus_cu_busy_o$16
+    connect \Y $616
   end
   process $group_273
     assign \wrflag_spr0_xer_so_3 1'0
-    assign \wrflag_spr0_xer_so_3 $651
+    assign \wrflag_spr0_xer_so_3 $616
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_mul0_xer_so_3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $653
+  wire width 1 $618
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $654
+  cell $and $619
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$154
-    connect \B \cu_busy_o$15
-    connect \Y $653
+    connect \A \fus_xer_so_ok$116
+    connect \B \fus_cu_busy_o$19
+    connect \Y $618
   end
   process $group_274
     assign \wrflag_mul0_xer_so_3 1'0
-    assign \wrflag_mul0_xer_so_3 $653
+    assign \wrflag_mul0_xer_so_3 $618
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $655
+  wire width 2 $620
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 1 $656
+  wire width 1 $621
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $657
+  cell $or $622
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest4_o$156
-    connect \B \fus_dest4_o$157
-    connect \Y $656
+    connect \A \fus_dest4_o$118
+    connect \B \fus_dest4_o$119
+    connect \Y $621
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 1 $658
+  wire width 1 $623
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $659
+  cell $or $624
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest5_o$155
-    connect \B $656
-    connect \Y $658
+    connect \A \fus_dest5_o$117
+    connect \B $621
+    connect \Y $623
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $pos $660
+  cell $pos $625
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 2
-    connect \A $658
-    connect \Y $655
+    connect \A $623
+    connect \Y $620
   end
   process $group_275
-    assign \xer_data_i$175 2'00
-    assign \xer_data_i$175 $655
+    assign \xer_data_i$140 2'00
+    assign \xer_data_i$140 $620
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  wire width 8 $661
+  wire width 8 $626
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  cell $sshl $662
+  cell $sshl $627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 8
     connect \A 1'1
-    connect \B \fasto1
-    connect \Y $661
+    connect \B \pdecode2_fasto1
+    connect \Y $626
   end
   process $group_276
     assign \fast_wen 8'00000000
@@ -157172,7 +156714,7 @@ module \core
     switch { \wrpick_FAST_fast1_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen $661
+        assign \fast_wen $626
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \fast_wen 8'00000000
@@ -157182,73 +156724,73 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_fast1_0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $663
+  wire width 1 $628
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $664
+  cell $and $629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_fast1_ok
-    connect \B \cu_busy_o$6
-    connect \Y $663
+    connect \B \fus_cu_busy_o$7
+    connect \Y $628
   end
   process $group_277
     assign \wrflag_branch0_fast1_0 1'0
-    assign \wrflag_branch0_fast1_0 $663
+    assign \wrflag_branch0_fast1_0 $628
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $665
+  wire width 1 $630
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $666
+  cell $and $631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$74 [0]
+    connect \A \fus_cu_wr__rel_o$120 [0]
     connect \B \fu_enable [2]
-    connect \Y $665
+    connect \Y $630
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $667
+  wire width 1 $632
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $668
+  cell $and $633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$55 [1]
+    connect \A \fus_cu_wr__rel_o$76 [1]
     connect \B \fu_enable [3]
-    connect \Y $667
+    connect \Y $632
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $669
+  wire width 1 $634
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $670
+  cell $and $635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [2]
+    connect \A \fus_cu_wr__rel_o$82 [2]
     connect \B \fu_enable [5]
-    connect \Y $669
+    connect \Y $634
   end
   process $group_278
     assign \wrpick_FAST_fast1_i 3'000
-    assign \wrpick_FAST_fast1_i [0] $665
-    assign \wrpick_FAST_fast1_i [1] $667
-    assign \wrpick_FAST_fast1_i [2] $669
+    assign \wrpick_FAST_fast1_i [0] $630
+    assign \wrpick_FAST_fast1_i [1] $632
+    assign \wrpick_FAST_fast1_i [2] $634
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $671
+  wire width 1 $636
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $672
+  cell $and $637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157256,12 +156798,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast1_o [0]
     connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $671
+    connect \Y $636
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $673
+  wire width 1 $638
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $674
+  cell $and $639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157269,12 +156811,12 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_fast2_o [0]
     connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $673
+    connect \Y $638
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $675
+  wire width 1 $640
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $676
+  cell $and $641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -157282,200 +156824,200 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \wrpick_FAST_nia_o [0]
     connect \B \wrpick_FAST_nia_en_o
-    connect \Y $675
+    connect \Y $640
   end
   process $group_279
-    assign \cu_wr__go_i$75 3'000
-    assign \cu_wr__go_i$75 [0] $671
-    assign \cu_wr__go_i$75 [1] $673
-    assign \cu_wr__go_i$75 [2] $675
+    assign \fus_cu_wr__go_i$121 3'000
+    assign \fus_cu_wr__go_i$121 [0] $636
+    assign \fus_cu_wr__go_i$121 [1] $638
+    assign \fus_cu_wr__go_i$121 [2] $640
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_fast1_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $677
+  wire width 1 $642
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $678
+  cell $and $643
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$158
-    connect \B \cu_busy_o$9
-    connect \Y $677
+    connect \A \fus_fast1_ok$122
+    connect \B \fus_cu_busy_o$10
+    connect \Y $642
   end
   process $group_280
     assign \wrflag_trap0_fast1_1 1'0
-    assign \wrflag_trap0_fast1_1 $677
+    assign \wrflag_trap0_fast1_1 $642
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_fast1_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $679
+  wire width 1 $644
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $680
+  cell $and $645
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$159
-    connect \B \cu_busy_o$13
-    connect \Y $679
+    connect \A \fus_fast1_ok$123
+    connect \B \fus_cu_busy_o$16
+    connect \Y $644
   end
   process $group_281
     assign \wrflag_spr0_fast1_2 1'0
-    assign \wrflag_spr0_fast1_2 $679
+    assign \wrflag_spr0_fast1_2 $644
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $681
+  wire width 64 $646
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $682
+  cell $or $647
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$160
-    connect \B \fus_dest3_o$161
-    connect \Y $681
+    connect \A \fus_dest2_o$125
+    connect \B \fus_dest3_o$126
+    connect \Y $646
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $683
+  wire width 64 $648
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $684
+  cell $or $649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \dest1_o$76
-    connect \B $681
-    connect \Y $683
+    connect \A \fus_dest1_o$124
+    connect \B $646
+    connect \Y $648
   end
   process $group_282
     assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i $683
+    assign \fast_data_i $648
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  wire width 8 $685
+  wire width 8 $650
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  cell $sshl $686
+  cell $sshl $651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 8
     connect \A 1'1
-    connect \B \fasto2
-    connect \Y $685
+    connect \B \pdecode2_fasto2
+    connect \Y $650
   end
   process $group_283
-    assign \fast_wen$176 8'00000000
+    assign \fast_wen$141 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_fast2_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen$176 $685
+        assign \fast_wen$141 $650
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \fast_wen$176 8'00000000
+        assign \fast_wen$141 8'00000000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_fast2_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $687
+  wire width 1 $652
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $688
+  cell $and $653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_fast2_ok
-    connect \B \cu_busy_o$6
-    connect \Y $687
+    connect \B \fus_cu_busy_o$7
+    connect \Y $652
   end
   process $group_284
     assign \wrflag_branch0_fast2_1 1'0
-    assign \wrflag_branch0_fast2_1 $687
+    assign \wrflag_branch0_fast2_1 $652
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $689
+  wire width 1 $654
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $690
+  cell $and $655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$74 [1]
+    connect \A \fus_cu_wr__rel_o$120 [1]
     connect \B \fu_enable [2]
-    connect \Y $689
+    connect \Y $654
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $691
+  wire width 1 $656
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $692
+  cell $and $657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$55 [2]
+    connect \A \fus_cu_wr__rel_o$76 [2]
     connect \B \fu_enable [3]
-    connect \Y $691
+    connect \Y $656
   end
   process $group_285
     assign \wrpick_FAST_fast2_i 2'00
-    assign \wrpick_FAST_fast2_i [0] $689
-    assign \wrpick_FAST_fast2_i [1] $691
+    assign \wrpick_FAST_fast2_i [0] $654
+    assign \wrpick_FAST_fast2_i [1] $656
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_fast2_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $693
+  wire width 1 $658
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $694
+  cell $and $659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok$162
-    connect \B \cu_busy_o$9
-    connect \Y $693
+    connect \A \fus_fast2_ok$127
+    connect \B \fus_cu_busy_o$10
+    connect \Y $658
   end
   process $group_286
     assign \wrflag_trap0_fast2_2 1'0
-    assign \wrflag_trap0_fast2_2 $693
+    assign \wrflag_trap0_fast2_2 $658
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $695
+  wire width 64 $660
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $696
+  cell $or $661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$163
-    connect \B \fus_dest3_o$164
-    connect \Y $695
+    connect \A \fus_dest2_o$128
+    connect \B \fus_dest3_o$129
+    connect \Y $660
   end
   process $group_287
-    assign \fast_data_i$177 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$177 $695
+    assign \fast_data_i$142 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$142 $660
     sync init
   end
   process $group_288
@@ -157494,147 +157036,147 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_branch0_nia_2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $697
+  wire width 1 $662
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $698
+  cell $and $663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_nia_ok
-    connect \B \cu_busy_o$6
-    connect \Y $697
+    connect \B \fus_cu_busy_o$7
+    connect \Y $662
   end
   process $group_289
     assign \wrflag_branch0_nia_2 1'0
-    assign \wrflag_branch0_nia_2 $697
+    assign \wrflag_branch0_nia_2 $662
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $699
+  wire width 1 $664
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $700
+  cell $and $665
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$74 [2]
+    connect \A \fus_cu_wr__rel_o$120 [2]
     connect \B \fu_enable [2]
-    connect \Y $699
+    connect \Y $664
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $701
+  wire width 1 $666
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $702
+  cell $and $667
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$55 [3]
+    connect \A \fus_cu_wr__rel_o$76 [3]
     connect \B \fu_enable [3]
-    connect \Y $701
+    connect \Y $666
   end
   process $group_290
     assign \wrpick_FAST_nia_i 2'00
-    assign \wrpick_FAST_nia_i [0] $699
-    assign \wrpick_FAST_nia_i [1] $701
+    assign \wrpick_FAST_nia_i [0] $664
+    assign \wrpick_FAST_nia_i [1] $666
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_nia_3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $703
+  wire width 1 $668
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $704
+  cell $and $669
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_nia_ok$165
-    connect \B \cu_busy_o$9
-    connect \Y $703
+    connect \A \fus_nia_ok$130
+    connect \B \fus_cu_busy_o$10
+    connect \Y $668
   end
   process $group_291
     assign \wrflag_trap0_nia_3 1'0
-    assign \wrflag_trap0_nia_3 $703
+    assign \wrflag_trap0_nia_3 $668
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $705
+  wire width 64 $670
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $706
+  cell $or $671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest3_o$166
-    connect \B \fus_dest4_o$167
-    connect \Y $705
+    connect \A \fus_dest3_o$131
+    connect \B \fus_dest4_o$132
+    connect \Y $670
   end
   process $group_292
-    assign \fast_data_i$178 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$178 $705
+    assign \fast_data_i$143 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$143 $670
     sync init
   end
   process $group_293
-    assign \fast_wen$179 8'00000000
+    assign \fast_wen$144 8'00000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
     switch { \wrpick_FAST_msr_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \fast_wen$179 8'00000010
+        assign \fast_wen$144 8'00000010
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
-        assign \fast_wen$179 8'00000000
+        assign \fast_wen$144 8'00000000
     end
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_trap0_msr_4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $707
+  wire width 1 $672
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $708
+  cell $and $673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_msr_ok
-    connect \B \cu_busy_o$9
-    connect \Y $707
+    connect \B \fus_cu_busy_o$10
+    connect \Y $672
   end
   process $group_294
     assign \wrflag_trap0_msr_4 1'0
-    assign \wrflag_trap0_msr_4 $707
+    assign \wrflag_trap0_msr_4 $672
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $709
+  wire width 1 $674
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $710
+  cell $and $675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$55 [4]
+    connect \A \fus_cu_wr__rel_o$76 [4]
     connect \B \fu_enable [3]
-    connect \Y $709
+    connect \Y $674
   end
   process $group_295
     assign \wrpick_FAST_msr_i 1'0
-    assign \wrpick_FAST_msr_i $709
+    assign \wrpick_FAST_msr_i $674
     sync init
   end
   process $group_296
-    assign \fast_data_i$180 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$180 \fus_dest5_o$168
+    assign \fast_data_i$145 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$145 \fus_dest5_o$133
     sync init
   end
   process $group_297
@@ -157643,7 +157185,7 @@ module \core
     switch { \wrpick_SPR_spr1_en_o }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
       case 1'1
-        assign \spr_dest__wen \spro [0]
+        assign \spr_dest__wen \pdecode2_spro [0]
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
       case
         assign \spr_dest__wen 1'0
@@ -157653,46 +157195,48 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
   wire width 1 \wrflag_spr0_spr1_1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $711
+  wire width 1 $676
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $712
+  cell $and $677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \fus_spr1_ok
-    connect \B \cu_busy_o$13
-    connect \Y $711
+    connect \B \fus_cu_busy_o$16
+    connect \Y $676
   end
   process $group_298
     assign \wrflag_spr0_spr1_1 1'0
-    assign \wrflag_spr0_spr1_1 $711
+    assign \wrflag_spr0_spr1_1 $676
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $713
+  wire width 1 $678
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $714
+  cell $and $679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__rel_o$59 [1]
+    connect \A \fus_cu_wr__rel_o$82 [1]
     connect \B \fu_enable [5]
-    connect \Y $713
+    connect \Y $678
   end
   process $group_299
     assign \wrpick_SPR_spr1_i 1'0
-    assign \wrpick_SPR_spr1_i $713
+    assign \wrpick_SPR_spr1_i $678
     sync init
   end
   process $group_300
     assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \spr_dest__data_i \fus_dest2_o$169
+    assign \spr_dest__data_i \fus_dest2_o$134
     sync init
   end
+  connect \o_ok 1'0
+  connect \ea_ok 1'0
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.imem"
@@ -157726,26 +157270,30 @@ module \imem
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 1 \ibus__stb$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 12 \ibus__dat_r
+  wire width 8 output 12 \ibus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 8 \ibus__sel$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 64 input 13 \ibus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 13 \ibus__adr
+  wire width 45 output 14 \ibus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
   wire width 45 \ibus__adr$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
-  wire width 1 input 14 \f_stall_i
+  wire width 1 input 15 \f_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 output 15 \f_fetch_err_o
+  wire width 1 output 16 \f_fetch_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
   wire width 1 \f_fetch_err_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 output 16 \f_badaddr_o
+  wire width 45 output 17 \f_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
   wire width 45 \f_badaddr_o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
-  wire width 1 output 17 \a_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  wire width 1 output 18 \a_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157753,9 +157301,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157814,7 +157362,7 @@ module \imem
           case 1'1
             assign \ibus__cyc$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
       case 2'1-
         assign \ibus__cyc$next 1'1
     end
@@ -157828,9 +157376,9 @@ module \imem
     sync posedge \clk
       update \ibus__cyc \ibus__cyc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157838,9 +157386,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157899,7 +157447,7 @@ module \imem
           case 1'1
             assign \ibus__stb$next 1'0
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
       case 2'1-
         assign \ibus__stb$next 1'1
     end
@@ -157913,13 +157461,9 @@ module \imem
     sync posedge \clk
       update \ibus__stb \ibus__stb$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
-  wire width 64 \ibus_rdata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
-  wire width 64 \ibus_rdata$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157927,9 +157471,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $and $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -157977,7 +157521,7 @@ module \imem
     connect \Y $29
   end
   process $group_2
-    assign \ibus_rdata$next \ibus_rdata
+    assign \ibus__sel$next \ibus__sel
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $23 \ibus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
@@ -157986,24 +157530,29 @@ module \imem
         switch { $29 }
           attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
           case 1'1
-            assign \ibus_rdata$next \ibus__dat_r
+            assign \ibus__sel$next 8'00000000
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
       case 2'1-
+        assign \ibus__sel$next 8'11111111
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \ibus__sel$next 8'00000000
     end
     sync init
-      update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \ibus__sel 8'00000000
     sync posedge \clk
-      update \ibus_rdata \ibus_rdata$next
+      update \ibus__sel \ibus__sel$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
+  wire width 64 \ibus_rdata
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
+  wire width 64 \ibus_rdata$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -158011,9 +157560,9 @@ module \imem
     connect \A \a_stall_i
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
   cell $and $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -158024,13 +157573,97 @@ module \imem
     connect \B $31
     connect \Y $33
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $36
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ibus__ack
+    connect \B \ibus__err
+    connect \Y $35
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $not $38
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \f_valid_i
+    connect \Y $37
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $40
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $35
+    connect \B $37
+    connect \Y $39
+  end
   process $group_3
-    assign \ibus__adr$next \ibus__adr
+    assign \ibus_rdata$next \ibus_rdata
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
     switch { $33 \ibus__cyc }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+        switch { $39 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+          case 1'1
+            assign \ibus_rdata$next \ibus__dat_r
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \clk
+      update \ibus_rdata \ibus_rdata$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $42
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a_stall_i
+    connect \Y $41
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $44
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a_valid_i
+    connect \B $41
+    connect \Y $43
+  end
+  process $group_4
+    assign \ibus__adr$next \ibus__adr
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $43 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
       case 2'1-
         assign \ibus__adr$next \a_pc_i [47:3]
     end
@@ -158044,10 +157677,10 @@ module \imem
     sync posedge \clk
       update \ibus__adr \ibus__adr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-  wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-  cell $and $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -158055,26 +157688,26 @@ module \imem
     parameter \Y_WIDTH 1
     connect \A \ibus__cyc
     connect \B \ibus__err
-    connect \Y $35
+    connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
-  wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
-  cell $not $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  cell $not $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \f_stall_i
-    connect \Y $37
+    connect \Y $47
   end
-  process $group_4
+  process $group_5
     assign \f_fetch_err_o$next \f_fetch_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-    switch { $37 $35 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+    switch { $47 $45 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
       case 2'-1
         assign \f_fetch_err_o$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
       case 2'1-
         assign \f_fetch_err_o$next 1'0
     end
@@ -158088,10 +157721,10 @@ module \imem
     sync posedge \clk
       update \f_fetch_err_o \f_fetch_err_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-  wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-  cell $and $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  cell $and $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -158099,26 +157732,26 @@ module \imem
     parameter \Y_WIDTH 1
     connect \A \ibus__cyc
     connect \B \ibus__err
-    connect \Y $39
+    connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
-  wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
-  cell $not $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  cell $not $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \f_stall_i
-    connect \Y $41
+    connect \Y $51
   end
-  process $group_5
+  process $group_6
     assign \f_badaddr_o$next \f_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
-    switch { $41 $39 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:74"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+    switch { $51 $49 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
       case 2'-1
         assign \f_badaddr_o$next \ibus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:79"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
       case 2'1-
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -158131,31 +157764,31 @@ module \imem
     sync posedge \clk
       update \f_badaddr_o \f_badaddr_o$next
   end
-  process $group_6
+  process $group_7
     assign \a_busy_o 1'0
     assign \a_busy_o \ibus__cyc
     sync init
   end
-  process $group_7
+  process $group_8
     assign \f_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
     switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
       case 1'1
         assign \f_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
       case
         assign \f_busy_o \ibus__cyc
     end
     sync init
   end
-  process $group_8
+  process $group_9
     assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
     switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:84"
-      case 1'1
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+      case 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
       case
         assign \f_instr_o \ibus_rdata
     end
@@ -158176,1961 +157809,114 @@ module \test_issuer
   wire width 1 input 3 \go_insn_i
   attribute \src "simple/issuer.py:56"
   wire width 1 input 4 \memerr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 5 \cu_rd__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 6 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 7 \cu_issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 8 \cu_shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 9 \cu_go_die_i
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 10 \oper_i_alu_alu0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 11 \oper_i_alu_alu0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 12 \oper_i_alu_alu0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 13 \oper_i_alu_alu0__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 14 \oper_i_alu_alu0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 15 \oper_i_alu_alu0__write_cr0
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 16 \oper_i_alu_alu0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 17 \oper_i_alu_alu0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 18 \oper_i_alu_alu0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 19 \oper_i_alu_alu0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 20 \oper_i_alu_alu0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 21 \oper_i_alu_alu0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 22 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 23 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 24 \cu_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 25 \cu_rd__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 26 \cu_wr__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 27 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 28 \cu_rd__go_i$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 29 \cu_wr__go_i$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 30 \cu_issue_i$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 31 \cu_shadown_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 32 \cu_go_die_i$5
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 33 \oper_i_alu_cr0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 34 \oper_i_alu_cr0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 35 \oper_i_alu_cr0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 36 \oper_i_alu_cr0__read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 37 \oper_i_alu_cr0__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 38 \src1_i$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 39 \src2_i$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 40 \cu_busy_o$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 41 \cu_rd__rel_o$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 42 \cu_wr__rel_o$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 43 \dest1_o$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 44 \cu_rd__go_i$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 45 \cu_wr__go_i$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 46 \cu_issue_i$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 47 \cu_shadown_i$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 48 \cu_go_die_i$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 49 \oper_i_alu_branch0__cia
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 50 \oper_i_alu_branch0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 51 \oper_i_alu_branch0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 52 \oper_i_alu_branch0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 53 \oper_i_alu_branch0__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 54 \oper_i_alu_branch0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 55 \src1_i$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 56 \src2_i$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 57 \cu_busy_o$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 58 \cu_rd__rel_o$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 59 \cu_wr__rel_o$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 60 \dest1_o$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 61 \cu_rd__go_i$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 62 \cu_wr__go_i$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 63 \cu_issue_i$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 64 \cu_shadown_i$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 65 \cu_go_die_i$27
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 66 \oper_i_alu_trap0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 67 \oper_i_alu_trap0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 68 \oper_i_alu_trap0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 69 \oper_i_alu_trap0__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 70 \oper_i_alu_trap0__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 71 \oper_i_alu_trap0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 5 output 72 \oper_i_alu_trap0__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 13 output 73 \oper_i_alu_trap0__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 74 \src1_i$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 75 \src2_i$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 76 \cu_busy_o$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 77 \cu_rd__rel_o$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 78 \cu_wr__rel_o$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 79 \dest1_o$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 80 \cu_rd__go_i$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 81 \cu_wr__go_i$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 82 \cu_issue_i$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 83 \cu_shadown_i$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 84 \cu_go_die_i$38
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 85 \oper_i_alu_logical0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 86 \oper_i_alu_logical0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 87 \oper_i_alu_logical0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 88 \oper_i_alu_logical0__zero_a
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 89 \oper_i_alu_logical0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 90 \oper_i_alu_logical0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 91 \oper_i_alu_logical0__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 92 \oper_i_alu_logical0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 93 \oper_i_alu_logical0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 94 \oper_i_alu_logical0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 95 \oper_i_alu_logical0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 96 \oper_i_alu_logical0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 97 \src1_i$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 98 \src2_i$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 99 \cu_busy_o$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 100 \cu_rd__rel_o$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 101 \cu_wr__rel_o$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 102 \dest1_o$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 103 \cu_rd__go_i$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 104 \cu_wr__go_i$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 105 \cu_issue_i$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 106 \cu_shadown_i$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 107 \cu_go_die_i$49
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 108 \oper_i_alu_spr0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 109 \oper_i_alu_spr0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 110 \oper_i_alu_spr0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 111 \oper_i_alu_spr0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 112 \src1_i$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 113 \src2_i$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 114 \cu_busy_o$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 115 \cu_rd__rel_o$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 116 \cu_wr__rel_o$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 117 \dest1_o$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 118 \cu_rd__go_i$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 119 \cu_wr__go_i$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 120 \cu_issue_i$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 121 \cu_shadown_i$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 122 \cu_go_die_i$60
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 123 \oper_i_alu_mul0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 124 \oper_i_alu_mul0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 125 \oper_i_alu_mul0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 126 \oper_i_alu_mul0__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 127 \oper_i_alu_mul0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 128 \oper_i_alu_mul0__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 129 \oper_i_alu_mul0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 130 \oper_i_alu_mul0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 131 \oper_i_alu_mul0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 132 \src1_i$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 133 \src2_i$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 134 \cu_busy_o$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 135 \cu_rd__rel_o$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 136 \cu_wr__rel_o$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 137 \dest1_o$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 138 \cu_rd__go_i$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 139 \cu_wr__go_i$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 140 \cu_issue_i$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 141 \cu_shadown_i$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 142 \cu_go_die_i$71
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 143 \oper_i_alu_shift_rot0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 144 \oper_i_alu_shift_rot0__fn_unit
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 146 \oper_i_alu_shift_rot0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 147 \oper_i_alu_shift_rot0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 148 \oper_i_alu_shift_rot0__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 149 \oper_i_alu_shift_rot0__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 150 \oper_i_alu_shift_rot0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 151 \oper_i_alu_shift_rot0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 152 \oper_i_alu_shift_rot0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 153 \src1_i$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 154 \src2_i$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 155 \cu_busy_o$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 156 \cu_rd__rel_o$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 157 \cu_wr__rel_o$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 158 \dest1_o$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 159 \cu_rd__go_i$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 160 \ad__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 161 \cu_wr__go_i$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 162 \st__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 output 163 \cu_issue_i$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 input 164 \cu_shadown_i$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 input 165 \cu_go_die_i$82
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 166 \oper_i_ldst_ldst0__insn_type
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 167 \oper_i_ldst_ldst0__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 168 \oper_i_ldst_ldst0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 169 \oper_i_ldst_ldst0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 output 170 \oper_i_ldst_ldst0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 171 \oper_i_ldst_ldst0__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 172 \oper_i_ldst_ldst0__sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 173 \oper_i_ldst_ldst0__ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 174 \src1_i$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 175 \src2_i$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 output 176 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 177 \cu_busy_o$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 178 \cu_rd__rel_o$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 179 \ad__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 180 \st__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 181 \cu_wr__rel_o$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 182 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 183 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 184 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 185 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
-  wire width 1 output 186 \load_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
-  wire width 1 output 187 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
-  wire width 32 output 188 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
-  wire width 1 input 189 \bigendian
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232"
-  wire width 32 output 190 \opcode_in
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
-  wire width 11 output 191 \function_unit
-  attribute \enum_base_type "In1Sel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "RA"
-  attribute \enum_value_010 "RA_OR_ZERO"
-  attribute \enum_value_011 "SPR"
-  attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
-  wire width 3 output 192 \in1_sel
-  attribute \enum_base_type "In2Sel"
-  attribute \enum_value_0000 "NONE"
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-  attribute \enum_value_0011 "CONST_SI"
-  attribute \enum_value_0100 "CONST_UI_HI"
-  attribute \enum_value_0101 "CONST_SI_HI"
-  attribute \enum_value_0110 "CONST_LI"
-  attribute \enum_value_0111 "CONST_BD"
-  attribute \enum_value_1000 "CONST_DS"
-  attribute \enum_value_1001 "CONST_M1"
-  attribute \enum_value_1010 "CONST_SH"
-  attribute \enum_value_1011 "CONST_SH32"
-  attribute \enum_value_1100 "SPR"
-  attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
-  wire width 4 output 193 \in2_sel
-  attribute \enum_base_type "In3Sel"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "RS"
-  attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
-  wire width 2 output 194 \in3_sel
-  attribute \enum_base_type "OutSel"
-  attribute \enum_value_00 "NONE"
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-  attribute \enum_value_10 "RA"
-  attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
-  wire width 2 output 195 \out_sel
-  attribute \enum_base_type "CRInSel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "CR0"
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-  attribute \enum_value_011 "BFA"
-  attribute \enum_value_100 "BA_BB"
-  attribute \enum_value_101 "BC"
-  attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
-  wire width 3 output 196 \cr_in
-  attribute \enum_base_type "CROutSel"
-  attribute \enum_value_000 "NONE"
-  attribute \enum_value_001 "CR0"
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-  attribute \enum_value_011 "BT"
-  attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
-  wire width 3 output 197 \cr_out
-  attribute \enum_base_type "LdstLen"
-  attribute \enum_value_0000 "NONE"
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-  attribute \enum_value_0100 "is4B"
-  attribute \enum_value_1000 "is8B"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
-  wire width 4 output 198 \ldst_len
-  attribute \enum_base_type "RC"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
-  wire width 2 output 199 \rc_sel
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
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-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
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-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
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-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
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-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
-  wire width 7 output 200 \internal_op
-  attribute \enum_base_type "Form"
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-  attribute \enum_value_00110 "DQ"
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-  attribute \enum_value_01001 "XL"
-  attribute \enum_value_01010 "XFX"
-  attribute \enum_value_01011 "XFL"
-  attribute \enum_value_01100 "XX1"
-  attribute \enum_value_01101 "XX2"
-  attribute \enum_value_01110 "XX3"
-  attribute \enum_value_01111 "XX4"
-  attribute \enum_value_10000 "XS"
-  attribute \enum_value_10001 "XO"
-  attribute \enum_value_10010 "A"
-  attribute \enum_value_10011 "M"
-  attribute \enum_value_10100 "MD"
-  attribute \enum_value_10101 "MDS"
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-  attribute \enum_value_11010 "EVS"
-  attribute \enum_value_11011 "Z22"
-  attribute \enum_value_11100 "Z23"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122"
-  wire width 5 output 201 \form
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
-  wire width 8 output 202 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 203 \inv_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 204 \inv_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 205 \cry_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 206 \br
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 207 \sgn_ext
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 208 \rsrv
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 209 \is_32b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 210 \sgn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 211 \lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137"
-  wire width 1 output 212 \sgl_pipe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
-  wire width 8 output 213 \asmcode$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 214 \rego
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 215 \rego_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 216 \ea$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 217 \ea_ok$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 218 \reg1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 219 \reg1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 220 \reg2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 221 \reg2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 5 output 222 \reg3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 223 \reg3_ok
-  attribute \enum_base_type "SPR"
-  attribute \enum_value_0000000001 "XER"
-  attribute \enum_value_0000000011 "DSCR"
-  attribute \enum_value_0000001000 "LR"
-  attribute \enum_value_0000001001 "CTR"
-  attribute \enum_value_0000001101 "AMR"
-  attribute \enum_value_0000010001 "DSCR_priv"
-  attribute \enum_value_0000010010 "DSISR"
-  attribute \enum_value_0000010011 "DAR"
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-  attribute \enum_value_0000011010 "SRR0"
-  attribute \enum_value_0000011011 "SRR1"
-  attribute \enum_value_0000011100 "CFAR"
-  attribute \enum_value_0000011101 "AMR_priv"
-  attribute \enum_value_0000110000 "PIDR"
-  attribute \enum_value_0000111101 "IAMR"
-  attribute \enum_value_0010000000 "TFHAR"
-  attribute \enum_value_0010000001 "TFIAR"
-  attribute \enum_value_0010000010 "TEXASR"
-  attribute \enum_value_0010000011 "TEXASRU"
-  attribute \enum_value_0010001000 "CTRL"
-  attribute \enum_value_0010010000 "TIDR"
-  attribute \enum_value_0010011000 "CTRL_priv"
-  attribute \enum_value_0010011001 "FSCR"
-  attribute \enum_value_0010011101 "UAMOR"
-  attribute \enum_value_0010011110 "GSR"
-  attribute \enum_value_0010011111 "PSPB"
-  attribute \enum_value_0010110000 "DPDES"
-  attribute \enum_value_0010110100 "DAWR0"
-  attribute \enum_value_0010111010 "RPR"
-  attribute \enum_value_0010111011 "CIABR"
-  attribute \enum_value_0010111100 "DAWRX0"
-  attribute \enum_value_0010111110 "HFSCR"
-  attribute \enum_value_0100000000 "VRSAVE"
-  attribute \enum_value_0100000011 "SPRG3"
-  attribute \enum_value_0100001100 "TB"
-  attribute \enum_value_0100001101 "TBU"
-  attribute \enum_value_0100010000 "SPRG0_priv"
-  attribute \enum_value_0100010001 "SPRG1_priv"
-  attribute \enum_value_0100010010 "SPRG2_priv"
-  attribute \enum_value_0100010011 "SPRG3_priv"
-  attribute \enum_value_0100011011 "CIR"
-  attribute \enum_value_0100011100 "TBL"
-  attribute \enum_value_0100011101 "TBU_hypv"
-  attribute \enum_value_0100011110 "TBU40"
-  attribute \enum_value_0100011111 "PVR"
-  attribute \enum_value_0100110000 "HSPRG0"
-  attribute \enum_value_0100110001 "HSPRG1"
-  attribute \enum_value_0100110010 "HDSISR"
-  attribute \enum_value_0100110011 "HDAR"
-  attribute \enum_value_0100110100 "SPURR"
-  attribute \enum_value_0100110101 "PURR"
-  attribute \enum_value_0100110110 "HDEC"
-  attribute \enum_value_0100111001 "HRMOR"
-  attribute \enum_value_0100111010 "HSRR0"
-  attribute \enum_value_0100111011 "HSRR1"
-  attribute \enum_value_0100111110 "LPCR"
-  attribute \enum_value_0100111111 "LPIDR"
-  attribute \enum_value_0101010000 "HMER"
-  attribute \enum_value_0101010001 "HMEER"
-  attribute \enum_value_0101010010 "PCR"
-  attribute \enum_value_0101010011 "HEIR"
-  attribute \enum_value_0101011101 "AMOR"
-  attribute \enum_value_0110111110 "TIR"
-  attribute \enum_value_0111010000 "PTCR"
-  attribute \enum_value_1100000000 "SIER"
-  attribute \enum_value_1100000001 "MMCR2"
-  attribute \enum_value_1100000010 "MMCRA"
-  attribute \enum_value_1100000011 "PMC1"
-  attribute \enum_value_1100000100 "PMC2"
-  attribute \enum_value_1100000101 "PMC3"
-  attribute \enum_value_1100000110 "PMC4"
-  attribute \enum_value_1100000111 "PMC5"
-  attribute \enum_value_1100001000 "PMC6"
-  attribute \enum_value_1100001011 "MMCR0"
-  attribute \enum_value_1100001100 "SIAR"
-  attribute \enum_value_1100001101 "SDAR"
-  attribute \enum_value_1100001110 "MMCR1"
-  attribute \enum_value_1100010000 "SIER_priv"
-  attribute \enum_value_1100010001 "MMCR2_priv"
-  attribute \enum_value_1100010010 "MMCRA_priv"
-  attribute \enum_value_1100010011 "PMC1_priv"
-  attribute \enum_value_1100010100 "PMC2_priv"
-  attribute \enum_value_1100010101 "PMC3_priv"
-  attribute \enum_value_1100010110 "PMC4_priv"
-  attribute \enum_value_1100010111 "PMC5_priv"
-  attribute \enum_value_1100011000 "PMC6_priv"
-  attribute \enum_value_1100011011 "MMCR0_priv"
-  attribute \enum_value_1100011100 "SIAR_priv"
-  attribute \enum_value_1100011101 "SDAR_priv"
-  attribute \enum_value_1100011110 "MMCR1_priv"
-  attribute \enum_value_1100100000 "BESCRS"
-  attribute \enum_value_1100100001 "BESCRSU"
-  attribute \enum_value_1100100010 "BESCRR"
-  attribute \enum_value_1100100011 "BESCRRU"
-  attribute \enum_value_1100100100 "EBBHR"
-  attribute \enum_value_1100100101 "EBBRR"
-  attribute \enum_value_1100100110 "BESCR"
-  attribute \enum_value_1100101000 "reserved808"
-  attribute \enum_value_1100101001 "reserved809"
-  attribute \enum_value_1100101010 "reserved810"
-  attribute \enum_value_1100101011 "reserved811"
-  attribute \enum_value_1100101111 "TAR"
-  attribute \enum_value_1100110000 "ASDR"
-  attribute \enum_value_1100110111 "PSSCR"
-  attribute \enum_value_1101010000 "IC"
-  attribute \enum_value_1101010001 "VTB"
-  attribute \enum_value_1101010111 "PSSCR_hypv"
-  attribute \enum_value_1110000000 "PPR"
-  attribute \enum_value_1110000010 "PPR32"
-  attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 10 output 224 \spro
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 225 \spro_ok
-  attribute \enum_base_type "SPR"
-  attribute \enum_value_0000000001 "XER"
-  attribute \enum_value_0000000011 "DSCR"
-  attribute \enum_value_0000001000 "LR"
-  attribute \enum_value_0000001001 "CTR"
-  attribute \enum_value_0000001101 "AMR"
-  attribute \enum_value_0000010001 "DSCR_priv"
-  attribute \enum_value_0000010010 "DSISR"
-  attribute \enum_value_0000010011 "DAR"
-  attribute \enum_value_0000010110 "DEC"
-  attribute \enum_value_0000011010 "SRR0"
-  attribute \enum_value_0000011011 "SRR1"
-  attribute \enum_value_0000011100 "CFAR"
-  attribute \enum_value_0000011101 "AMR_priv"
-  attribute \enum_value_0000110000 "PIDR"
-  attribute \enum_value_0000111101 "IAMR"
-  attribute \enum_value_0010000000 "TFHAR"
-  attribute \enum_value_0010000001 "TFIAR"
-  attribute \enum_value_0010000010 "TEXASR"
-  attribute \enum_value_0010000011 "TEXASRU"
-  attribute \enum_value_0010001000 "CTRL"
-  attribute \enum_value_0010010000 "TIDR"
-  attribute \enum_value_0010011000 "CTRL_priv"
-  attribute \enum_value_0010011001 "FSCR"
-  attribute \enum_value_0010011101 "UAMOR"
-  attribute \enum_value_0010011110 "GSR"
-  attribute \enum_value_0010011111 "PSPB"
-  attribute \enum_value_0010110000 "DPDES"
-  attribute \enum_value_0010110100 "DAWR0"
-  attribute \enum_value_0010111010 "RPR"
-  attribute \enum_value_0010111011 "CIABR"
-  attribute \enum_value_0010111100 "DAWRX0"
-  attribute \enum_value_0010111110 "HFSCR"
-  attribute \enum_value_0100000000 "VRSAVE"
-  attribute \enum_value_0100000011 "SPRG3"
-  attribute \enum_value_0100001100 "TB"
-  attribute \enum_value_0100001101 "TBU"
-  attribute \enum_value_0100010000 "SPRG0_priv"
-  attribute \enum_value_0100010001 "SPRG1_priv"
-  attribute \enum_value_0100010010 "SPRG2_priv"
-  attribute \enum_value_0100010011 "SPRG3_priv"
-  attribute \enum_value_0100011011 "CIR"
-  attribute \enum_value_0100011100 "TBL"
-  attribute \enum_value_0100011101 "TBU_hypv"
-  attribute \enum_value_0100011110 "TBU40"
-  attribute \enum_value_0100011111 "PVR"
-  attribute \enum_value_0100110000 "HSPRG0"
-  attribute \enum_value_0100110001 "HSPRG1"
-  attribute \enum_value_0100110010 "HDSISR"
-  attribute \enum_value_0100110011 "HDAR"
-  attribute \enum_value_0100110100 "SPURR"
-  attribute \enum_value_0100110101 "PURR"
-  attribute \enum_value_0100110110 "HDEC"
-  attribute \enum_value_0100111001 "HRMOR"
-  attribute \enum_value_0100111010 "HSRR0"
-  attribute \enum_value_0100111011 "HSRR1"
-  attribute \enum_value_0100111110 "LPCR"
-  attribute \enum_value_0100111111 "LPIDR"
-  attribute \enum_value_0101010000 "HMER"
-  attribute \enum_value_0101010001 "HMEER"
-  attribute \enum_value_0101010010 "PCR"
-  attribute \enum_value_0101010011 "HEIR"
-  attribute \enum_value_0101011101 "AMOR"
-  attribute \enum_value_0110111110 "TIR"
-  attribute \enum_value_0111010000 "PTCR"
-  attribute \enum_value_1100000000 "SIER"
-  attribute \enum_value_1100000001 "MMCR2"
-  attribute \enum_value_1100000010 "MMCRA"
-  attribute \enum_value_1100000011 "PMC1"
-  attribute \enum_value_1100000100 "PMC2"
-  attribute \enum_value_1100000101 "PMC3"
-  attribute \enum_value_1100000110 "PMC4"
-  attribute \enum_value_1100000111 "PMC5"
-  attribute \enum_value_1100001000 "PMC6"
-  attribute \enum_value_1100001011 "MMCR0"
-  attribute \enum_value_1100001100 "SIAR"
-  attribute \enum_value_1100001101 "SDAR"
-  attribute \enum_value_1100001110 "MMCR1"
-  attribute \enum_value_1100010000 "SIER_priv"
-  attribute \enum_value_1100010001 "MMCR2_priv"
-  attribute \enum_value_1100010010 "MMCRA_priv"
-  attribute \enum_value_1100010011 "PMC1_priv"
-  attribute \enum_value_1100010100 "PMC2_priv"
-  attribute \enum_value_1100010101 "PMC3_priv"
-  attribute \enum_value_1100010110 "PMC4_priv"
-  attribute \enum_value_1100010111 "PMC5_priv"
-  attribute \enum_value_1100011000 "PMC6_priv"
-  attribute \enum_value_1100011011 "MMCR0_priv"
-  attribute \enum_value_1100011100 "SIAR_priv"
-  attribute \enum_value_1100011101 "SDAR_priv"
-  attribute \enum_value_1100011110 "MMCR1_priv"
-  attribute \enum_value_1100100000 "BESCRS"
-  attribute \enum_value_1100100001 "BESCRSU"
-  attribute \enum_value_1100100010 "BESCRR"
-  attribute \enum_value_1100100011 "BESCRRU"
-  attribute \enum_value_1100100100 "EBBHR"
-  attribute \enum_value_1100100101 "EBBRR"
-  attribute \enum_value_1100100110 "BESCR"
-  attribute \enum_value_1100101000 "reserved808"
-  attribute \enum_value_1100101001 "reserved809"
-  attribute \enum_value_1100101010 "reserved810"
-  attribute \enum_value_1100101011 "reserved811"
-  attribute \enum_value_1100101111 "TAR"
-  attribute \enum_value_1100110000 "ASDR"
-  attribute \enum_value_1100110111 "PSSCR"
-  attribute \enum_value_1101010000 "IC"
-  attribute \enum_value_1101010001 "VTB"
-  attribute \enum_value_1101010111 "PSSCR_hypv"
-  attribute \enum_value_1110000000 "PPR"
-  attribute \enum_value_1110000010 "PPR32"
-  attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 10 output 226 \spr1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 227 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
-  wire width 1 output 228 \xer_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83"
-  wire width 1 output 229 \xer_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 230 \fast1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 231 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 232 \fast2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 233 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 234 \fasto1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 235 \fasto1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 236 \fasto2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 237 \fasto2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 238 \cr_in1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 239 \cr_in1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 240 \cr_in2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 241 \cr_in2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 242 \cr_in2$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 243 \cr_in2_ok$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 244 \cr_out$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 245 \cr_out_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
-  wire width 64 output 246 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
-  wire width 64 output 247 \cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
-  wire width 32 output 248 \insn
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
-  wire width 7 output 249 \insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40"
-  wire width 11 output 250 \fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 251 \imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 252 \imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
-  wire width 1 output 253 \lk$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 254 \rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 255 \rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 256 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 257 \oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
-  wire width 1 output 258 \invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
-  wire width 1 output 259 \zero_a
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
-  wire width 2 output 260 \input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
-  wire width 1 output 261 \output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
-  wire width 1 output 262 \input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
-  wire width 1 output 263 \output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
-  wire width 1 output 264 \invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
-  wire width 1 output 265 \is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
-  wire width 1 output 266 \is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
-  wire width 4 output 267 \data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
-  wire width 1 output 268 \byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
-  wire width 1 output 269 \sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
-  wire width 2 output 270 \ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
-  wire width 5 output 271 \traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
-  wire width 13 output 272 \trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
-  wire width 1 output 273 \read_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
-  wire width 1 output 274 \write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
-  wire width 1 output 275 \write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 276 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 277 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 278 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 279 \ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 output 280 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 output 281 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 282 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 283 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 284 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 285 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 286 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 287 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 288 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 289 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 290 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 291 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 292 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 293 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 input 294 \x_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 295 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 input 296 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 297 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 298 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 output 299 \m_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 300 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 output 301 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 output 302 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 output 303 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 304 \dbus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 305 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 306 \dbus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 307 \dbus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 308 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 309 \dbus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 310 \dbus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 311 \dbus__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 3 input 312 \dbus__cti
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 2 input 313 \dbus__bte
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 314 \dbus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 315 \ldst_port0_is_ld_i$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 316 \ldst_port0_is_st_i$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 317 \ldst_port0_data_len$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 318 \ldst_port0_busy_o$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 input 319 \ldst_port0_go_die_i$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 320 \ldst_port0_addr_i$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 321 \ldst_port0_addr_i_ok$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 322 \ldst_port0_addr_ok_o$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 output 323 \ldst_port0_addr_exc_o$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 324 \ldst_port0_ld_data_o$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 325 \ldst_port0_ld_data_o_ok$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 326 \ldst_port0_st_data_i$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 327 \ldst_port0_st_data_i_ok$107
+  attribute \src "simple/issuer.py:51"
+  wire width 1 output 5 \core_start_i
+  attribute \src "simple/issuer.py:52"
+  wire width 1 output 6 \core_stop_i
+  attribute \src "simple/issuer.py:53"
+  wire width 1 output 7 \core_bigendian_i
+  attribute \src "simple/issuer.py:54"
+  wire width 1 output 8 \busy_o
+  attribute \src "simple/issuer.py:55"
+  wire width 1 output 9 \halted_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
-  wire width 48 output 328 \a_pc_i
+  wire width 48 output 10 \a_pc_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
-  wire width 1 input 329 \a_stall_i
+  wire width 1 input 11 \a_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
-  wire width 1 output 330 \a_valid_i
+  wire width 1 output 12 \a_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
-  wire width 1 input 331 \f_stall_i
+  wire width 1 input 13 \f_stall_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
-  wire width 1 output 332 \f_valid_i
+  wire width 1 output 14 \f_valid_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
-  wire width 1 output 333 \a_busy_o
+  wire width 1 output 15 \a_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
-  wire width 1 output 334 \f_busy_o
+  wire width 1 output 16 \f_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
-  wire width 64 output 335 \f_instr_o
+  wire width 64 output 17 \f_instr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 output 336 \f_fetch_err_o
+  wire width 1 output 18 \f_fetch_err_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 output 337 \f_badaddr_o
+  wire width 45 output 19 \f_badaddr_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 338 \ibus__adr
+  wire width 45 output 20 \ibus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 339 \ibus__dat_w
+  wire width 64 input 21 \ibus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 340 \ibus__dat_r
+  wire width 64 input 22 \ibus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 input 341 \ibus__sel
+  wire width 8 output 23 \ibus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 342 \ibus__cyc
+  wire width 1 output 24 \ibus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 343 \ibus__stb
+  wire width 1 output 25 \ibus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 344 \ibus__ack
+  wire width 1 input 26 \ibus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 345 \ibus__we
+  wire width 1 input 27 \ibus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 3 input 346 \ibus__cti
+  wire width 3 input 28 \ibus__cti
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 2 input 347 \ibus__bte
+  wire width 2 input 29 \ibus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 348 \ibus__err
-  attribute \src "simple/issuer.py:51"
-  wire width 1 output 349 \core_start_i
-  attribute \src "simple/issuer.py:52"
-  wire width 1 output 350 \core_stop_i
-  attribute \src "simple/issuer.py:53"
-  wire width 1 output 351 \core_bigendian_i
-  attribute \src "simple/issuer.py:54"
-  wire width 1 output 352 \busy_o
-  attribute \src "simple/issuer.py:55"
-  wire width 1 output 353 \halted_o
+  wire width 1 input 30 \ibus__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 output 31 \x_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 output 32 \x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 output 33 \x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 output 34 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 output 35 \x_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+  wire width 1 input 36 \x_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 output 37 \x_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+  wire width 1 input 38 \m_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 output 39 \m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 output 40 \x_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+  wire width 1 output 41 \m_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 output 42 \m_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 output 43 \m_load_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 output 44 \m_store_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 output 45 \m_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 45 output 46 \dbus__adr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 output 47 \dbus__dat_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 input 48 \dbus__dat_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 8 output 49 \dbus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 50 \dbus__cyc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 51 \dbus__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 52 \dbus__ack
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 53 \dbus__we
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 3 input 54 \dbus__cti
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 2 input 55 \dbus__bte
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 56 \dbus__err
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 354 \clk
+  wire width 1 input 57 \clk
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 355 \rst
+  wire width 1 input 58 \rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
   wire width 1 \core_corebusy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
@@ -160139,6 +157925,16 @@ module \test_issuer
   wire width 1 \core_core_start_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
   wire width 1 \core_core_stop_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+  wire width 1 \core_bigendian
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 \core_cu_ad__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 \core_cu_ad__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 \core_cu_st__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 \core_cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -160147,6 +157943,8 @@ module \test_issuer
   wire width 1 \core_valid
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
   wire width 1 \core_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
+  wire width 32 \core_raw_opcode_in
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -160155,6 +157953,81 @@ module \test_issuer
   wire width 64 \core_msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
   wire width 64 \core_cia
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+  wire width 7 \core_insn_type
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 8 \core_fast_nia_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -160166,324 +158039,35 @@ module \test_issuer
     connect \core_terminated_o \core_core_terminated_o
     connect \core_start_i \core_core_start_i
     connect \core_stop_i \core_core_stop_i
-    connect \bigendian \bigendian
-    connect \ad__go_i \ad__go_i
-    connect \ad__rel_o \ad__rel_o
-    connect \st__go_i \st__go_i
-    connect \st__rel_o \st__rel_o
+    connect \bigendian \core_bigendian
+    connect \cu_ad__go_i \core_cu_ad__go_i
+    connect \cu_ad__rel_o \core_cu_ad__rel_o
+    connect \cu_st__go_i \core_cu_st__go_i
+    connect \cu_st__rel_o \core_cu_st__rel_o
     connect \cia__ren \core_cia__ren
     connect \cia__data_o \core_cia__data_o
     connect \valid \core_valid
     connect \issue_i \core_issue_i
-    connect \raw_opcode_in \raw_opcode_in
+    connect \raw_opcode_in \core_raw_opcode_in
     connect \msr__ren \core_msr__ren
     connect \msr__data_o \core_msr__data_o
     connect \msr \core_msr
     connect \cia \core_cia
-    connect \insn_type \insn_type
+    connect \insn_type \core_insn_type
     connect \fast_nia_wen \core_fast_nia_wen
     connect \wen \core_wen
     connect \data_i \core_data_i
     connect \rst \rst
     connect \clk \clk
-    connect \fn_unit \fn_unit
-    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
-    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
-    connect \imm \imm
-    connect \imm_ok \imm_ok
-    connect \rc \rc
-    connect \rc_ok \rc_ok
-    connect \oe \oe
-    connect \oe_ok \oe_ok
-    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
-    connect \invert_a \invert_a
-    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
-    connect \zero_a \zero_a
-    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
-    connect \invert_out \invert_out
-    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
-    connect \write_cr0 \write_cr0
-    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
-    connect \input_carry \input_carry
-    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
-    connect \output_carry \output_carry
-    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
-    connect \is_32bit \is_32bit
-    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
-    connect \is_signed \is_signed
-    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
-    connect \data_len \data_len
-    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
-    connect \insn \insn
-    connect \cu_issue_i \cu_issue_i
-    connect \cu_busy_o \cu_busy_o
-    connect \reg1_ok \reg1_ok
-    connect \reg2_ok \reg2_ok
-    connect \xer_in \xer_in
-    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
-    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
-    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
-    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
-    connect \read_cr_whole \read_cr_whole
-    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
-    connect \write_cr_whole \write_cr_whole
-    connect \cu_issue_i$1 \cu_issue_i$3
-    connect \cu_busy_o$2 \cu_busy_o$8
-    connect \cr_in1_ok \cr_in1_ok
-    connect \cr_in2_ok \cr_in2_ok
-    connect \cr_in2_ok$3 \cr_in2_ok$92
-    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
-    connect \cia$4 \cia
-    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
-    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
-    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
-    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
-    connect \lk \lk$94
-    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
-    connect \cu_issue_i$5 \cu_issue_i$14
-    connect \cu_busy_o$6 \cu_busy_o$19
-    connect \fast1_ok \fast1_ok
-    connect \fast2_ok \fast2_ok
-    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
-    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
-    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
-    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
-    connect \msr$7 \msr
-    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
-    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
-    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
-    connect \traptype \traptype
-    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
-    connect \trapaddr \trapaddr
-    connect \cu_issue_i$8 \cu_issue_i$25
-    connect \cu_busy_o$9 \cu_busy_o$30
-    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
-    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
-    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
-    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
-    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
-    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
-    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
-    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
-    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
-    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
-    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
-    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
-    connect \cu_issue_i$10 \cu_issue_i$36
-    connect \cu_busy_o$11 \cu_busy_o$41
-    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
-    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
-    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
-    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
-    connect \cu_issue_i$12 \cu_issue_i$47
-    connect \cu_busy_o$13 \cu_busy_o$52
-    connect \spr1_ok \spr1_ok
-    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
-    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
-    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
-    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
-    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
-    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
-    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
-    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
-    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
-    connect \cu_issue_i$14 \cu_issue_i$58
-    connect \cu_busy_o$15 \cu_busy_o$63
-    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
-    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
-    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
-    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
-    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
-    connect \input_cr \input_cr
-    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
-    connect \output_cr \output_cr
-    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
-    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
-    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
-    connect \cu_issue_i$16 \cu_issue_i$69
-    connect \cu_busy_o$17 \cu_busy_o$74
-    connect \reg3_ok \reg3_ok
-    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
-    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
-    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
-    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
-    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
-    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
-    connect \byte_reverse \byte_reverse
-    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
-    connect \sign_extend \sign_extend
-    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
-    connect \ldst_mode \ldst_mode
-    connect \cu_issue_i$18 \cu_issue_i$80
-    connect \cu_busy_o$19 \cu_busy_o$85
-    connect \reg1 \reg1
-    connect \cu_rd__rel_o \cu_rd__rel_o
-    connect \cu_rd__go_i \cu_rd__go_i
-    connect \src1_i \src1_i
-    connect \cu_rd__rel_o$20 \cu_rd__rel_o$9
-    connect \cu_rd__go_i$21 \cu_rd__go_i$1
-    connect \src1_i$22 \src1_i$6
-    connect \cu_rd__rel_o$23 \cu_rd__rel_o$31
-    connect \cu_rd__go_i$24 \cu_rd__go_i$23
-    connect \src1_i$25 \src1_i$28
-    connect \cu_rd__rel_o$26 \cu_rd__rel_o$42
-    connect \cu_rd__go_i$27 \cu_rd__go_i$34
-    connect \src1_i$28 \src1_i$39
-    connect \cu_rd__rel_o$29 \cu_rd__rel_o$53
-    connect \cu_rd__go_i$30 \cu_rd__go_i$45
-    connect \src1_i$31 \src1_i$50
-    connect \cu_rd__rel_o$32 \cu_rd__rel_o$64
-    connect \cu_rd__go_i$33 \cu_rd__go_i$56
-    connect \src1_i$34 \src1_i$61
-    connect \cu_rd__rel_o$35 \cu_rd__rel_o$75
-    connect \cu_rd__go_i$36 \cu_rd__go_i$67
-    connect \src1_i$37 \src1_i$72
-    connect \cu_rd__rel_o$38 \cu_rd__rel_o$86
-    connect \cu_rd__go_i$39 \cu_rd__go_i$78
-    connect \src1_i$40 \src1_i$83
-    connect \reg2 \reg2
-    connect \src2_i \src2_i
-    connect \src2_i$41 \src2_i$7
-    connect \src2_i$42 \src2_i$29
-    connect \src2_i$43 \src2_i$40
-    connect \src2_i$44 \src2_i$62
-    connect \src2_i$45 \src2_i$73
-    connect \src2_i$46 \src2_i$84
-    connect \reg3 \reg3
-    connect \src3_i \src3_i
-    connect \cr_in1 \cr_in1
-    connect \cu_rd__rel_o$47 \cu_rd__rel_o$20
-    connect \cu_rd__go_i$48 \cu_rd__go_i$12
-    connect \cr_in2 \cr_in2
-    connect \cr_in2$49 \cr_in2$91
-    connect \fast1 \fast1
-    connect \src1_i$50 \src1_i$17
-    connect \fast2 \fast2
-    connect \src2_i$51 \src2_i$18
-    connect \spr1 \spr1
-    connect \src2_i$52 \src2_i$51
-    connect \rego \rego
-    connect \cu_wr__rel_o \cu_wr__rel_o
-    connect \cu_wr__go_i \cu_wr__go_i
-    connect \cu_wr__rel_o$53 \cu_wr__rel_o$10
-    connect \cu_wr__go_i$54 \cu_wr__go_i$2
-    connect \cu_wr__rel_o$55 \cu_wr__rel_o$32
-    connect \cu_wr__go_i$56 \cu_wr__go_i$24
-    connect \cu_wr__rel_o$57 \cu_wr__rel_o$43
-    connect \cu_wr__go_i$58 \cu_wr__go_i$35
-    connect \cu_wr__rel_o$59 \cu_wr__rel_o$54
-    connect \cu_wr__go_i$60 \cu_wr__go_i$46
-    connect \cu_wr__rel_o$61 \cu_wr__rel_o$65
-    connect \cu_wr__go_i$62 \cu_wr__go_i$57
-    connect \cu_wr__rel_o$63 \cu_wr__rel_o$76
-    connect \cu_wr__go_i$64 \cu_wr__go_i$68
-    connect \o_ok \o_ok
-    connect \cu_wr__rel_o$65 \cu_wr__rel_o$87
-    connect \cu_wr__go_i$66 \cu_wr__go_i$79
-    connect \dest1_o \dest1_o
-    connect \dest1_o$67 \dest1_o$11
-    connect \dest1_o$68 \dest1_o$33
-    connect \dest1_o$69 \dest1_o$44
-    connect \dest1_o$70 \dest1_o$55
-    connect \dest1_o$71 \dest1_o$66
-    connect \dest1_o$72 \dest1_o$77
-    connect \o \o
-    connect \ea \ea$89
-    connect \ea_ok \ea_ok
-    connect \ea$73 \ea
-    connect \cr_out \cr_out$93
-    connect \fasto1 \fasto1
-    connect \cu_wr__rel_o$74 \cu_wr__rel_o$21
-    connect \cu_wr__go_i$75 \cu_wr__go_i$13
-    connect \dest1_o$76 \dest1_o$22
-    connect \fasto2 \fasto2
-    connect \spro \spro
-    connect \opcode_in \opcode_in
-    connect \in1_sel \in1_sel
-    connect \in2_sel \in2_sel
-    connect \in3_sel \in3_sel
-    connect \out_sel \out_sel
-    connect \rc_sel \rc_sel
-    connect \cr_in \cr_in
-    connect \cr_out$77 \cr_out
-    connect \internal_op \internal_op
-    connect \function_unit \function_unit
-    connect \rego_ok \rego_ok
-    connect \ea_ok$78 \ea_ok$90
-    connect \spro_ok \spro_ok
-    connect \fasto1_ok \fasto1_ok
-    connect \fasto2_ok \fasto2_ok
-    connect \cr_out_ok \cr_out_ok
-    connect \ldst_len \ldst_len
-    connect \inv_a \inv_a
-    connect \inv_out \inv_out
-    connect \cry_out \cry_out
-    connect \is_32b \is_32b
-    connect \sgn \sgn
-    connect \lk$79 \lk
-    connect \br \br
-    connect \sgn_ext \sgn_ext
-    connect \xer_out \xer_out
-    connect \asmcode \asmcode$88
-    connect \form \form
-    connect \rsrv \rsrv
-    connect \sgl_pipe \sgl_pipe
-    connect \asmcode$80 \asmcode
-    connect \cu_go_die_i \cu_go_die_i
-    connect \cu_shadown_i \cu_shadown_i
-    connect \cu_go_die_i$81 \cu_go_die_i$5
-    connect \cu_shadown_i$82 \cu_shadown_i$4
-    connect \cu_go_die_i$83 \cu_go_die_i$16
-    connect \cu_shadown_i$84 \cu_shadown_i$15
-    connect \cu_go_die_i$85 \cu_go_die_i$27
-    connect \cu_shadown_i$86 \cu_shadown_i$26
-    connect \cu_go_die_i$87 \cu_go_die_i$38
-    connect \cu_shadown_i$88 \cu_shadown_i$37
-    connect \cu_go_die_i$89 \cu_go_die_i$49
-    connect \cu_shadown_i$90 \cu_shadown_i$48
-    connect \cu_go_die_i$91 \cu_go_die_i$60
-    connect \cu_shadown_i$92 \cu_shadown_i$59
-    connect \cu_go_die_i$93 \cu_go_die_i$71
-    connect \cu_shadown_i$94 \cu_shadown_i$70
-    connect \cu_go_die_i$95 \cu_go_die_i$82
-    connect \load_mem_o \load_mem_o
-    connect \stwd_mem_o \stwd_mem_o
-    connect \cu_shadown_i$96 \cu_shadown_i$81
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$95
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i$96
-    connect \ldst_port0_data_len \ldst_port0_data_len$97
-    connect \ldst_port0_addr_i \ldst_port0_addr_i$100
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$101
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$103
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$102
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$104
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$105
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i$106
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$107
-    connect \ldst_port0_is_ld_i$97 \ldst_port0_is_ld_i
-    connect \ldst_port0_busy_o \ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$98 \ldst_port0_is_st_i
-    connect \ldst_port0_data_len$99 \ldst_port0_data_len
-    connect \ldst_port0_addr_i$100 \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok$101 \ldst_port0_addr_i_ok
     connect \x_mask_i \x_mask_i
     connect \x_addr_i \x_addr_i
-    connect \ldst_port0_addr_ok_o$102 \ldst_port0_addr_ok_o
     connect \m_ld_data_o \m_ld_data_o
-    connect \ldst_port0_ld_data_o$103 \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok$104 \ldst_port0_ld_data_o_ok
     connect \x_busy_o \x_busy_o
-    connect \ldst_port0_st_data_i_ok$105 \ldst_port0_st_data_i_ok
-    connect \ldst_port0_st_data_i$106 \ldst_port0_st_data_i
     connect \x_st_data_i \x_st_data_i
-    connect \ldst_port0_addr_exc_o$107 \ldst_port0_addr_exc_o
     connect \x_ld_i \x_ld_i
     connect \x_st_i \x_st_i
     connect \m_valid_i \m_valid_i
     connect \x_valid_i \x_valid_i
-    connect \ldst_port0_go_die_i \ldst_port0_go_die_i
-    connect \ldst_port0_go_die_i$108 \ldst_port0_go_die_i$99
-    connect \ldst_port0_busy_o$109 \ldst_port0_busy_o$98
     connect \dbus__cyc \dbus__cyc
     connect \x_stall_i \x_stall_i
     connect \dbus__ack \dbus__ack
@@ -160513,6 +158097,7 @@ module \test_issuer
     connect \ibus__ack \ibus__ack
     connect \ibus__err \ibus__err
     connect \ibus__stb \ibus__stb
+    connect \ibus__sel \ibus__sel
     connect \ibus__dat_r \ibus__dat_r
     connect \ibus__adr \ibus__adr
     connect \f_stall_i \f_stall_i
@@ -160542,17 +158127,17 @@ module \test_issuer
   end
   process $group_4
     assign \core_bigendian_i 1'0
-    assign \core_bigendian_i \bigendian
+    assign \core_bigendian_i \core_bigendian
     sync init
   end
   process $group_5
-    assign \ad__go_i 1'0
-    assign \ad__go_i \ad__rel_o
+    assign \core_cu_ad__go_i 1'0
+    assign \core_cu_ad__go_i \core_cu_ad__rel_o
     sync init
   end
   process $group_6
-    assign \st__go_i 1'0
-    assign \st__go_i \st__rel_o
+    assign \core_cu_st__go_i 1'0
+    assign \core_cu_st__go_i \core_cu_st__rel_o
     sync init
   end
   attribute \src "simple/issuer.py:89"
@@ -160567,11 +158152,11 @@ module \test_issuer
   attribute \src "simple/issuer.py:99"
   wire width 64 \nia
   attribute \src "simple/issuer.py:100"
-  wire width 65 $108
+  wire width 65 $1
   attribute \src "simple/issuer.py:100"
-  wire width 65 $109
+  wire width 65 $2
   attribute \src "simple/issuer.py:100"
-  cell $add $110
+  cell $add $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -160579,12 +158164,12 @@ module \test_issuer
     parameter \Y_WIDTH 65
     connect \A \cur_pc
     connect \B 3'100
-    connect \Y $109
+    connect \Y $2
   end
-  connect $108 $109
+  connect $1 $2
   process $group_8
     assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \nia $108 [63:0]
+    assign \nia $1 [63:0]
     sync init
   end
   attribute \src "simple/issuer.py:90"
@@ -160592,33 +158177,33 @@ module \test_issuer
   attribute \src "simple/issuer.py:90"
   wire width 1 \pc_changed$next
   attribute \src "simple/issuer.py:114"
-  wire width 1 $111
+  wire width 1 $4
   attribute \src "simple/issuer.py:114"
-  cell $not $112
+  cell $not $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $111
+    connect \Y $4
   end
   attribute \src "simple/issuer.py:121"
   wire width 2 \fsm_state
   attribute \src "simple/issuer.py:121"
   wire width 2 \fsm_state$next
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $113
+  wire width 1 $6
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $114
+  cell $reduce_bool $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \core_fast_nia_wen
-    connect \Y $113
+    connect \Y $6
   end
   process $group_9
     assign \pc_changed$next \pc_changed
     attribute \src "simple/issuer.py:114"
-    switch { $111 }
+    switch { $4 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160640,7 +158225,7 @@ module \test_issuer
               attribute \src "simple/issuer.py:179"
               case
                 attribute \src "simple/issuer.py:185"
-                switch { $113 }
+                switch { $6 }
                   attribute \src "simple/issuer.py:185"
                   case 1'1
                     assign \pc_changed$next 1'1
@@ -160661,19 +158246,19 @@ module \test_issuer
   attribute \src "simple/issuer.py:128"
   wire width 64 \pc
   attribute \src "simple/issuer.py:114"
-  wire width 1 $115
+  wire width 1 $8
   attribute \src "simple/issuer.py:114"
-  cell $not $116
+  cell $not $9
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $115
+    connect \Y $8
   end
   process $group_10
     assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $115 }
+    switch { $8 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160706,19 +158291,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $117
+  wire width 1 $10
   attribute \src "simple/issuer.py:114"
-  cell $not $118
+  cell $not $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $117
+    connect \Y $10
   end
   process $group_11
     assign \core_cia__ren 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $117 }
+    switch { $10 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160750,19 +158335,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $119
+  wire width 1 $12
   attribute \src "simple/issuer.py:114"
-  cell $not $120
+  cell $not $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $119
+    connect \Y $12
   end
   process $group_12
     assign \a_pc_i 48'000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $119 }
+    switch { $12 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160787,19 +158372,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $121
+  wire width 1 $14
   attribute \src "simple/issuer.py:114"
-  cell $not $122
+  cell $not $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $121
+    connect \Y $14
   end
   process $group_13
     assign \a_valid_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $121 }
+    switch { $14 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160832,19 +158417,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $123
+  wire width 1 $16
   attribute \src "simple/issuer.py:114"
-  cell $not $124
+  cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $123
+    connect \Y $16
   end
   process $group_14
     assign \f_valid_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $123 }
+    switch { $16 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160877,19 +158462,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $125
+  wire width 1 $18
   attribute \src "simple/issuer.py:114"
-  cell $not $126
+  cell $not $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $125
+    connect \Y $18
   end
   process $group_15
     assign \cur_pc$next \cur_pc
     attribute \src "simple/issuer.py:114"
-    switch { $125 }
+    switch { $18 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160922,29 +158507,29 @@ module \test_issuer
       update \cur_pc \cur_pc$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $127
+  wire width 1 $20
   attribute \src "simple/issuer.py:114"
-  cell $not $128
+  cell $not $21
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $127
+    connect \Y $20
   end
   attribute \src "simple/issuer.py:187"
-  wire width 1 $129
+  wire width 1 $22
   attribute \src "simple/issuer.py:187"
-  cell $not $130
+  cell $not $23
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $129
+    connect \Y $22
   end
   process $group_16
     assign \fsm_state$next \fsm_state
     attribute \src "simple/issuer.py:114"
-    switch { $127 }
+    switch { $20 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -160980,7 +158565,7 @@ module \test_issuer
               attribute \src "simple/issuer.py:179"
               case
                 attribute \src "simple/issuer.py:187"
-                switch { $129 }
+                switch { $22 }
                   attribute \src "simple/issuer.py:187"
                   case 1'1
                     assign \fsm_state$next 2'00
@@ -161001,21 +158586,21 @@ module \test_issuer
   attribute \src "simple/issuer.py:88"
   wire width 32 \current_insn
   attribute \src "simple/issuer.py:114"
-  wire width 1 $131
+  wire width 1 $24
   attribute \src "simple/issuer.py:114"
-  cell $not $132
+  cell $not $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $131
+    connect \Y $24
   end
   attribute \src "simple/issuer.py:157"
-  wire width 32 $133
+  wire width 32 $26
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  wire width 7 $134
+  wire width 7 $27
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $135
+  cell $mul $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -161023,23 +158608,23 @@ module \test_issuer
     parameter \Y_WIDTH 7
     connect \A \cur_pc [2]
     connect \B 6'100000
-    connect \Y $134
+    connect \Y $27
   end
   attribute \src "simple/issuer.py:157"
-  cell $shift $136
+  cell $shift $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 32
     connect \A \f_instr_o
-    connect \B $134
-    connect \Y $133
+    connect \B $27
+    connect \Y $26
   end
   process $group_17
     assign \current_insn 32'00000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $131 }
+    switch { $24 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161056,7 +158641,7 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \current_insn $133
+                assign \current_insn $26
             end
           attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
@@ -161066,32 +158651,32 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $137
+  wire width 1 $30
   attribute \src "simple/issuer.py:114"
-  cell $not $138
+  cell $not $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $137
+    connect \Y $30
   end
   attribute \src "simple/issuer.py:180"
-  wire width 1 $139
+  wire width 1 $32
   attribute \src "simple/issuer.py:180"
-  cell $ne $140
+  cell $ne $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \insn_type
+    connect \A \core_insn_type
     connect \B 7'0000001
-    connect \Y $139
+    connect \Y $32
   end
   process $group_18
     assign \core_valid 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $137 }
+    switch { $30 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161120,7 +158705,7 @@ module \test_issuer
               attribute \src "simple/issuer.py:179"
               case
                 attribute \src "simple/issuer.py:180"
-                switch { $139 }
+                switch { $32 }
                   attribute \src "simple/issuer.py:180"
                   case 1'1
                     assign \core_valid 1'1
@@ -161131,19 +158716,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $141
+  wire width 1 $34
   attribute \src "simple/issuer.py:114"
-  cell $not $142
+  cell $not $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $141
+    connect \Y $34
   end
   process $group_19
     assign \core_issue_i 1'0
     attribute \src "simple/issuer.py:114"
-    switch { $141 }
+    switch { $34 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161170,23 +158755,23 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $143
+  wire width 1 $36
   attribute \src "simple/issuer.py:114"
-  cell $not $144
+  cell $not $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $143
+    connect \Y $36
   end
   attribute \src "simple/issuer.py:92"
   wire width 32 \ilatch
   attribute \src "simple/issuer.py:92"
   wire width 32 \ilatch$next
   process $group_20
-    assign \raw_opcode_in 32'00000000000000000000000000000000
+    assign \core_raw_opcode_in 32'00000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $143 }
+    switch { $36 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161203,7 +158788,7 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \raw_opcode_in \current_insn
+                assign \core_raw_opcode_in \current_insn
             end
           attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
@@ -161214,26 +158799,26 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:179"
               case
-                assign \raw_opcode_in \ilatch
+                assign \core_raw_opcode_in \ilatch
             end
         end
     end
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $145
+  wire width 1 $38
   attribute \src "simple/issuer.py:114"
-  cell $not $146
+  cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $145
+    connect \Y $38
   end
   process $group_21
     assign \ilatch$next \ilatch
     attribute \src "simple/issuer.py:114"
-    switch { $145 }
+    switch { $38 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161268,19 +158853,19 @@ module \test_issuer
       update \ilatch \ilatch$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $147
+  wire width 1 $40
   attribute \src "simple/issuer.py:114"
-  cell $not $148
+  cell $not $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $147
+    connect \Y $40
   end
   process $group_22
     assign \core_msr__ren 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $147 }
+    switch { $40 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161307,21 +158892,21 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:96"
-  wire width 64 \msr$149
+  wire width 64 \msr
   attribute \src "simple/issuer.py:114"
-  wire width 1 $150
+  wire width 1 $42
   attribute \src "simple/issuer.py:114"
-  cell $not $151
+  cell $not $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $150
+    connect \Y $42
   end
   process $group_23
-    assign \msr$149 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $150 }
+    switch { $42 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161338,7 +158923,7 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \msr$149 \core_msr__data_o
+                assign \msr \core_msr__data_o
             end
           attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
@@ -161348,14 +158933,14 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $152
+  wire width 1 $44
   attribute \src "simple/issuer.py:114"
-  cell $not $153
+  cell $not $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $152
+    connect \Y $44
   end
   attribute \src "simple/issuer.py:95"
   wire width 64 \cur_msr
@@ -161364,7 +158949,7 @@ module \test_issuer
   process $group_24
     assign \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $152 }
+    switch { $44 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161381,7 +158966,7 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \core_msr \msr$149
+                assign \core_msr \msr
             end
           attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
@@ -161399,19 +158984,19 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $154
+  wire width 1 $46
   attribute \src "simple/issuer.py:114"
-  cell $not $155
+  cell $not $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $154
+    connect \Y $46
   end
   process $group_25
     assign \cur_msr$next \cur_msr
     attribute \src "simple/issuer.py:114"
-    switch { $154 }
+    switch { $46 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161428,7 +159013,7 @@ module \test_issuer
               case 1'1
               attribute \src "simple/issuer.py:151"
               case
-                assign \cur_msr$next \msr$149
+                assign \cur_msr$next \msr
             end
           attribute \src "simple/issuer.py:176"
           attribute \nmigen.decoding "INSN_ACTIVE/2"
@@ -161446,19 +159031,19 @@ module \test_issuer
       update \cur_msr \cur_msr$next
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $156
+  wire width 1 $48
   attribute \src "simple/issuer.py:114"
-  cell $not $157
+  cell $not $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $156
+    connect \Y $48
   end
   process $group_26
     assign \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $156 }
+    switch { $48 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161493,39 +159078,39 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $158
+  wire width 1 $50
   attribute \src "simple/issuer.py:114"
-  cell $not $159
+  cell $not $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $158
+    connect \Y $50
   end
   attribute \src "simple/issuer.py:187"
-  wire width 1 $160
+  wire width 1 $52
   attribute \src "simple/issuer.py:187"
-  cell $not $161
+  cell $not $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $160
+    connect \Y $52
   end
   attribute \src "simple/issuer.py:191"
-  wire width 1 $162
+  wire width 1 $54
   attribute \src "simple/issuer.py:191"
-  cell $not $163
+  cell $not $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $162
+    connect \Y $54
   end
   process $group_27
     assign \core_wen 8'00000000
     attribute \src "simple/issuer.py:114"
-    switch { $158 }
+    switch { $50 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161546,11 +159131,11 @@ module \test_issuer
               attribute \src "simple/issuer.py:179"
               case
                 attribute \src "simple/issuer.py:187"
-                switch { $160 }
+                switch { $52 }
                   attribute \src "simple/issuer.py:187"
                   case 1'1
                     attribute \src "simple/issuer.py:191"
-                    switch { $162 }
+                    switch { $54 }
                       attribute \src "simple/issuer.py:191"
                       case 1'1
                         assign \core_wen 8'00000001
@@ -161562,39 +159147,39 @@ module \test_issuer
     sync init
   end
   attribute \src "simple/issuer.py:114"
-  wire width 1 $164
+  wire width 1 $56
   attribute \src "simple/issuer.py:114"
-  cell $not $165
+  cell $not $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_core_terminated_o
-    connect \Y $164
+    connect \Y $56
   end
   attribute \src "simple/issuer.py:187"
-  wire width 1 $166
+  wire width 1 $58
   attribute \src "simple/issuer.py:187"
-  cell $not $167
+  cell $not $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $166
+    connect \Y $58
   end
   attribute \src "simple/issuer.py:191"
-  wire width 1 $168
+  wire width 1 $60
   attribute \src "simple/issuer.py:191"
-  cell $not $169
+  cell $not $61
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $168
+    connect \Y $60
   end
   process $group_28
     assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "simple/issuer.py:114"
-    switch { $164 }
+    switch { $56 }
       attribute \src "simple/issuer.py:114"
       case 1'1
         attribute \src "simple/issuer.py:121"
@@ -161615,11 +159200,11 @@ module \test_issuer
               attribute \src "simple/issuer.py:179"
               case
                 attribute \src "simple/issuer.py:187"
-                switch { $166 }
+                switch { $58 }
                   attribute \src "simple/issuer.py:187"
                   case 1'1
                     attribute \src "simple/issuer.py:191"
-                    switch { $168 }
+                    switch { $60 }
                       attribute \src "simple/issuer.py:191"
                       case 1'1
                         assign \core_data_i \nia
@@ -161632,4 +159217,5 @@ module \test_issuer
   end
   connect \core_core_start_i 1'0
   connect \core_core_stop_i 1'0
+  connect \core_bigendian 1'0
 end
-- 
2.30.2