From 313027b4929fe46639860aea195202aef4b680af Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 10 Feb 2020 10:05:53 -0500 Subject: [PATCH] Fix flake8 errors in part_cmp/ --- src/ieee754/part_cmp/eq_gt_ge.py | 9 ++++----- src/ieee754/part_cmp/gt_combiner.py | 7 ++++--- src/ieee754/part_cmp/reorder_results.py | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/ieee754/part_cmp/eq_gt_ge.py b/src/ieee754/part_cmp/eq_gt_ge.py index 4614776d..4cc8a0ef 100644 --- a/src/ieee754/part_cmp/eq_gt_ge.py +++ b/src/ieee754/part_cmp/eq_gt_ge.py @@ -15,14 +15,12 @@ See: * http://bugs.libre-riscv.org/show_bug.cgi?id=171 """ -from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl -from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.cli import main, rtlil +from nmigen import Signal, Module, Elaboratable, Cat, C +from nmigen.back.pysim import Simulator, Delay from ieee754.part_mul_add.partpoints import PartitionPoints from ieee754.part_cmp.gt_combiner import GTCombiner from ieee754.part_cmp.reorder_results import ReorderResults -from ieee754.part_cmp.ripple import RippleLSB class PartitionedEqGtGe(Elaboratable): @@ -47,7 +45,7 @@ class PartitionedEqGtGe(Elaboratable): self.mwidth = len(self.partition_points)+1 self.output = Signal(self.mwidth, reset_less=True) assert self.partition_points.fits_in_width(width), \ - "partition_points doesn't fit in width" + "partition_points doesn't fit in width" def elaborate(self, platform): m = Module() @@ -110,6 +108,7 @@ class PartitionedEqGtGe(Elaboratable): self.partition_points.as_sig(), self.output] + if __name__ == "__main__": from ieee754.part_mul_add.partpoints import make_partition m = Module() diff --git a/src/ieee754/part_cmp/gt_combiner.py b/src/ieee754/part_cmp/gt_combiner.py index 2828cd16..05082028 100644 --- a/src/ieee754/part_cmp/gt_combiner.py +++ b/src/ieee754/part_cmp/gt_combiner.py @@ -1,5 +1,5 @@ from nmigen import Signal, Module, Elaboratable, Mux -from ieee754.part_mul_add.partpoints import PartitionPoints + class Combiner(Elaboratable): @@ -28,6 +28,7 @@ class Combiner(Elaboratable): # equal flag is set AND the previous partition's greater than output # is true + class GTCombiner(Elaboratable): def __init__(self, width): @@ -46,8 +47,8 @@ class GTCombiner(Elaboratable): self.aux_input = Signal(reset_less=True) # right hand side mux input self.gt_en = Signal(reset_less=True) # enable or disable gt signal - self.eqs = Signal(width, reset_less=True) # the flags for EQ - self.gts = Signal(width, reset_less=True) # the flags for GT + self.eqs = Signal(width, reset_less=True) # the flags for EQ + self.gts = Signal(width, reset_less=True) # the flags for GT self.gates = Signal(width-1, reset_less=True) self.outputs = Signal(width, reset_less=True) diff --git a/src/ieee754/part_cmp/reorder_results.py b/src/ieee754/part_cmp/reorder_results.py index 41c64652..e1a03476 100644 --- a/src/ieee754/part_cmp/reorder_results.py +++ b/src/ieee754/part_cmp/reorder_results.py @@ -3,7 +3,7 @@ # bits need to be reversed through the width of the partition. This # module does that from nmigen import Signal, Module, Elaboratable, Mux -from ieee754.part_mul_add.partpoints import PartitionPoints + class ReorderResults(Elaboratable): def __init__(self, width): -- 2.30.2