From 3159690c5f6aee9844747228b29c7b281cdd787e Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 21 Jun 2019 22:20:32 +0100 Subject: [PATCH] --- simple_v_extension/specification.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 47303ea93..5c0ed23ef 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -81,10 +81,11 @@ The principle of SV is as follows: * A "Vector Length" CSR is set, indicating the span of any future "parallel" operations. * If any operation (a **scalar** standard RV opcode) - uses a register that has been so "marked", + uses a register that has been so "marked" + ("tagged"), a hardware "macro-unrolling loop" is activated, of length VL, that effectively issues **multiple** identical instructions - using contiguous sequentially-incrementing register numbers. + using contiguous sequentially-incrementing register numbers, based on the "tags". * **Whether they be executed sequentially or in parallel or a mixture of both or punted to software-emulation in a trap handler is entirely up to the implementor**. -- 2.30.2