From 315b2bef11f2ee53ccb209763bdcfce87b9eb43c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 24 Mar 2011 17:35:01 -0700 Subject: [PATCH] alpha: Unify movdi patterns with enabled attribute. From-SVN: r171437 --- gcc/ChangeLog | 6 +++ gcc/config/alpha/alpha.md | 84 ++++++--------------------------------- 2 files changed, 19 insertions(+), 71 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eaed8bf135a..a523f45c44e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2011-02-24 Richard Henderson + + * config/alpha/alpha.md (attribute isa): Add er, ner. + (attribute enabled): Handle them. + (*movdi): Merge *movdi_{er_nofix,nofix,er_fix,fix}. + 2011-02-24 Richard Henderson * config/alpha/alpha.md (attribute isa): Add vms. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 0f712922f59..2161e64adbd 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -181,7 +181,7 @@ ;; Used to control the "enabled" attribute on a per-instruction basis. ;; For convenience, conflate ABI issues re loading of addresses with ;; an "isa". -(define_attr "isa" "base,bwx,max,fix,cix,vms" +(define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" (const_string "base")) (define_attr "enabled" "" @@ -189,7 +189,9 @@ (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") - (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") + (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") + (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") + (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") ] (const_int 1))) @@ -4869,54 +4871,13 @@ operands[2] = pic_offset_table_rtx; }) -(define_insn "*movdi_er_nofix" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q") - (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))] - "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX - && (register_operand (operands[0], DImode) - || reg_or_0_operand (operands[1], DImode))" - "@ - mov %r1,%0 - lda %0,%1($31) - ldah %0,%h1($31) - # - # - # - ldq%A1 %0,%1 - stq%A0 %r1,%0 - fmov %R1,%0 - ldt %0,%1 - stt %R1,%0" - [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst") - (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")]) - -(define_insn "*movdi_nofix" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q") - (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f"))] - "! TARGET_FIX - && (register_operand (operands[0], DImode) - || reg_or_0_operand (operands[1], DImode))" - "@ - bis $31,%r1,%0 - lda %0,%1($31) - ldah %0,%h1($31) - lda %0,%1 - # - ldq%A1 %0,%1 - stq%A0 %r1,%0 - cpys %R1,%R1,%0 - ldt %0,%1 - stt %R1,%0" - [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")]) - -(define_insn "*movdi_er_fix" +(define_insn "*movdi" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") + "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") (match_operand:DI 1 "input_operand" - "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))] - "TARGET_EXPLICIT_RELOCS && TARGET_FIX - && (register_operand (operands[0], DImode) - || reg_or_0_operand (operands[1], DImode))" + "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] + "register_operand (operands[0], DImode) + || reg_or_0_operand (operands[1], DImode)" "@ mov %r1,%0 lda %0,%1($31) @@ -4924,36 +4885,17 @@ # # # - ldq%A1 %0,%1 - stq%A0 %r1,%0 - fmov %R1,%0 - ldt %0,%1 - stt %R1,%0 - ftoit %1,%0 - itoft %1,%0" - [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof") - (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")]) - -(define_insn "*movdi_fix" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f") - (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))] - "! TARGET_EXPLICIT_RELOCS && TARGET_FIX - && (register_operand (operands[0], DImode) - || reg_or_0_operand (operands[1], DImode))" - "@ - bis $31,%r1,%0 - lda %0,%1($31) - ldah %0,%h1($31) lda %0,%1 - # ldq%A1 %0,%1 stq%A0 %r1,%0 - cpys %R1,%R1,%0 + fmov %R1,%0 ldt %0,%1 stt %R1,%0 ftoit %1,%0 itoft %1,%0" - [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")]) + [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") + (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") + (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) ;; VMS needs to set up "vms_base_regno" for unwinding. This move ;; often appears dead to the life analysis code, at which point we -- 2.30.2