From 316b0dd2fa604d1635bb473f36e6a6a77fe73a58 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 21 Jul 2023 18:46:17 -0700 Subject: [PATCH] add SVP64 tests for cfuged, cntlzdm, cnttzdm, pdepd, and pextd --- openpower/isatables/RM-1P-2S1D.csv | 10 +- src/openpower/sv/sv_analysis.py | 4 + src/openpower/test/logical/svp64_cases.py | 156 ++++++++++++++++++++++ 3 files changed, 165 insertions(+), 5 deletions(-) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index f61cd27f..b70d617c 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -15,16 +15,16 @@ cmpeqb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 1/0=fcmpo,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0 4/0=ftdiv,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0 bmask,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 -cntlzdm,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 -pdepd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 +cntlzdm,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 +pdepd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 addex,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 -pextd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 -cfuged,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 +pextd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 +cfuged,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 bpermd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 modud,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 moduw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 cmpb,CROP,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 -cnttzdm,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0 +cnttzdm,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0 modsd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 modsw,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0 26/6=fmrgow,NORMAL,,1P,EXTRA3,NO,d:FRT,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,0,0 diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index f9a74a58..61b97d69 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -568,6 +568,10 @@ def extra_classifier(insn_name, value, name, res, regs): res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3 res['2'] = 's:RB' # RB: Rsrc1_EXTRA3 + elif regs == ['RS', 'RB', '', 'RA', '', '']: + res['0'] = 'd:RA' # RA: Rdest1_EXTRA3 + res['1'] = 's:RS' # RS: Rsrc1_EXTRA3 + res['2'] = 's:RB' # RB: Rsrc1_EXTRA3 elif name == '2R-1W' or insn_name == 'cmpb': # cmpb if insn_name in ['bpermd', 'cmpb']: res['0'] = 'd:RA' # RA: Rdest1_EXTRA3 diff --git a/src/openpower/test/logical/svp64_cases.py b/src/openpower/test/logical/svp64_cases.py index cd5665e5..f937155d 100644 --- a/src/openpower/test/logical/svp64_cases.py +++ b/src/openpower/test/logical/svp64_cases.py @@ -1,3 +1,5 @@ +from nmutil.sim_util import hash_256 +from openpower.test.state import ExpectedState from openpower.test.common import TestAccumulatorBase, skip_case from openpower.endian import bigendian from openpower.simulator.program import Program @@ -387,3 +389,157 @@ class SVP64LogicalTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_svstate=svstate) + + def case_cfuged(self): + prog = Program(list(SVP64Asm(["sv.cfuged *10,*20,*30"])), bigendian) + for case_idx in range(50): + VL = 5 + svstate = SVP64State() + svstate.vl = VL + svstate.maxvl = VL + gprs = [0] * 128 + for elidx in range(VL): + k = f"sv.cfuged {case_idx} {elidx}" + gprs[20 + elidx] = hash_256(f"{k} r20") % 2**64 + gprs[30 + elidx] = hash_256(f"{k} r30") % 2**64 + e = ExpectedState(pc=8, int_regs=gprs) + for elidx in range(VL): + zeros = [] + ones = [] + for i in range(64): + bit = 1 << i + if gprs[30 + elidx] & bit: + ones.append(bool(gprs[20 + elidx] & bit)) + else: + zeros.append(bool(gprs[20 + elidx] & bit)) + bits = ones + zeros + e.intregs[10 + elidx] = 0 + for i, v in enumerate(bits): + e.intregs[10 + elidx] |= v << i + with self.subTest( + case_idx=case_idx, + RS_in=[hex(gprs[20 + i]) for i in range(VL)], + RB_in=[hex(gprs[30 + i]) for i in range(VL)], + expected_RA=[hex(e.intregs[10 + i]) for i in range(VL)], + ): + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def case_cntlzdm(self): + prog = Program(list(SVP64Asm(["sv.cntlzdm *10,*20,*30"])), bigendian) + for case_idx in range(200): + VL = 5 + svstate = SVP64State() + svstate.vl = VL + svstate.maxvl = VL + gprs = [0] * 128 + for elidx in range(VL): + k = f"sv.cntlzdm {case_idx} {elidx}" + gprs[20 + elidx] = hash_256(f"{k} r20") % 2**64 + gprs[30 + elidx] = hash_256(f"{k} r30") % 2**64 + e = ExpectedState(pc=8, int_regs=gprs) + for elidx in range(VL): + count = 0 + for i in reversed(range(64)): + bit = 1 << i + if gprs[30 + elidx] & bit: + if gprs[20 + elidx] & bit: + break + count += 1 + e.intregs[10 + elidx] = count + with self.subTest( + case_idx=case_idx, + RS_in=[hex(gprs[20 + i]) for i in range(VL)], + RB_in=[hex(gprs[30 + i]) for i in range(VL)], + expected_RA=[hex(e.intregs[10 + i]) for i in range(VL)], + ): + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def case_cnttzdm(self): + prog = Program(list(SVP64Asm(["sv.cnttzdm *10,*20,*30"])), bigendian) + for case_idx in range(200): + VL = 5 + svstate = SVP64State() + svstate.vl = VL + svstate.maxvl = VL + gprs = [0] * 128 + for elidx in range(VL): + k = f"sv.cnttzdm {case_idx} {elidx}" + gprs[20 + elidx] = hash_256(f"{k} r20") % 2**64 + gprs[30 + elidx] = hash_256(f"{k} r30") % 2**64 + e = ExpectedState(pc=8, int_regs=gprs) + for elidx in range(VL): + count = 0 + for i in range(64): + bit = 1 << i + if gprs[30 + elidx] & bit: + if gprs[20 + elidx] & bit: + break + count += 1 + e.intregs[10 + elidx] = count + with self.subTest( + case_idx=case_idx, + RS_in=[hex(gprs[20 + i]) for i in range(VL)], + RB_in=[hex(gprs[30 + i]) for i in range(VL)], + expected_RA=[hex(e.intregs[10 + i]) for i in range(VL)], + ): + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def case_pdepd(self): + prog = Program(list(SVP64Asm(["sv.pdepd *10,*20,*30"])), bigendian) + for case_idx in range(200): + VL = 5 + svstate = SVP64State() + svstate.vl = VL + svstate.maxvl = VL + gprs = [0] * 128 + for elidx in range(VL): + k = f"sv.pdepd {case_idx} {elidx}" + gprs[20 + elidx] = hash_256(f"{k} r20") % 2**64 + gprs[30 + elidx] = hash_256(f"{k} r30") % 2**64 + e = ExpectedState(pc=8, int_regs=gprs) + for elidx in range(VL): + e.intregs[10 + elidx] = 0 + j = 0 + for i in range(64): + bit = 1 << i + if gprs[30 + elidx] & bit: + if gprs[20 + elidx] & (1 << j): + e.intregs[10 + elidx] |= bit + j += 1 + with self.subTest( + case_idx=case_idx, + RS_in=[hex(gprs[20 + i]) for i in range(VL)], + RB_in=[hex(gprs[30 + i]) for i in range(VL)], + expected_RA=[hex(e.intregs[10 + i]) for i in range(VL)], + ): + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def case_pextd(self): + prog = Program(list(SVP64Asm(["sv.pextd *10,*20,*30"])), bigendian) + for case_idx in range(200): + VL = 5 + svstate = SVP64State() + svstate.vl = VL + svstate.maxvl = VL + gprs = [0] * 128 + for elidx in range(VL): + k = f"sv.pextd {case_idx} {elidx}" + gprs[20 + elidx] = hash_256(f"{k} r20") % 2**64 + gprs[30 + elidx] = hash_256(f"{k} r30") % 2**64 + e = ExpectedState(pc=8, int_regs=gprs) + for elidx in range(VL): + e.intregs[10 + elidx] = 0 + j = 0 + for i in range(64): + bit = 1 << i + if gprs[30 + elidx] & bit: + if gprs[20 + elidx] & bit: + e.intregs[10 + elidx] |= 1 << j + j += 1 + with self.subTest( + case_idx=case_idx, + RS_in=[hex(gprs[20 + i]) for i in range(VL)], + RB_in=[hex(gprs[30 + i]) for i in range(VL)], + expected_RA=[hex(e.intregs[10 + i]) for i in range(VL)], + ): + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) -- 2.30.2