From 31826f7ce22019bb8b3ecfdc3ab104b3799ec9e3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 16:00:12 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 563b57e85..d6b82ea93 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -56,9 +56,9 @@ to not overburden implementors with features that they do not need. *There is no dependence between the two types of Compliancy Levels* The resources below therefore are not all required for all SV Compliancy Levels but -they are all required +they are all required to be reserved. -# Simple-V Resources +# Simple-V Architectural Resources * No new Interrupt types are required. * GPR FPR and CR Field Register numbers are extended to 128. @@ -74,7 +74,15 @@ they are all required * To hold all Vector Context, five SPRs are needed for userspace (MSR.PR=1 Problem State). If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly need five SPRs each. -* Six 5/6-bit XO "Management" instructions are needed. +* Six 5/6-bit XO (A-Form) "Management" instructions are needed. + +**Summary of Opcode space** + +* 75% of one Major Opcode (equivalent to the rest of EXT017) +* Six 5/6-bit operations. + +No further opcode space *for Simple-V* is envisaged to be required for at least +the next decade. **SPRs** @@ -86,6 +94,10 @@ they are all required with SVLR by SV-Branch-Conditional for exactly the same reason that NIA is swapped with LR +* Management Instructions + +**setvl** + # SVP64 24-bit Prefix The SVP64 24-bit Prefix provides several options -- 2.30.2