From 319646231162aa597892f515677e9b0c78e49865 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 12 Dec 2013 23:17:51 +0100 Subject: [PATCH] add support for Verilog include paths --- mibuild/generic_platform.py | 4 ++++ mibuild/xilinx_ise.py | 18 ++++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index f6e097bb..284d0f5e 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -148,6 +148,7 @@ class GenericPlatform: name = self.__module__.split(".")[-1] self.name = name self.sources = [] + self.verilog_include_paths = [] self.finalized = False def request(self, *args, **kwargs): @@ -195,6 +196,9 @@ class GenericPlatform: if language is not None: self.add_source(os.path.join(root, filename), language) + def add_verilog_include_path(self, path): + self.verilog_include_paths.append(os.path.abspath(path)) + def _resolve_signals(self, vns): # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 37eb329c..4bfca827 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -70,7 +70,7 @@ def _build_ucf(named_sc, named_pc): r += "\n" + "\n\n".join(named_pc) return r -def _build_xst_files(device, sources, build_name, xst_opt): +def _build_xst_files(device, sources, vincpaths, build_name, xst_opt): prj_contents = "" for filename, language in sources: prj_contents += language + " work " + filename + "\n" @@ -81,13 +81,19 @@ def _build_xst_files(device, sources, build_name, xst_opt): -top top {xst_opt} -ofn {build_name}.ngc --p {device}""".format(build_name=build_name, xst_opt=xst_opt, device=device) +-p {device} +""".format(build_name=build_name, xst_opt=xst_opt, device=device) + for path in vincpaths: + xst_contents += "-vlgincdir " + path + "\n" tools.write_to_file(build_name + ".xst", xst_contents) -def _run_yosys(device, sources, build_name): +def _run_yosys(device, sources, vincpaths, build_name): ys_contents = "" + incflags = "" + for path in vincpaths: + incflags += " -I" + path for filename, language in sources: - ys_contents += "read_{} {}\n".format(language, filename) + ys_contents += "read_{}{} {}\n".format(language, incflags, filename) if device[:2] == "xc": archcode = device[2:4] @@ -212,10 +218,10 @@ class XilinxISEPlatform(GenericPlatform): tools.write_to_file(v_file, v_src) sources = self.sources + [(v_file, "verilog")] if mode == "xst": - _build_xst_files(self.device, sources, build_name, self.xst_opt) + _build_xst_files(self.device, sources, self.verilog_include_paths, build_name, self.xst_opt) isemode = "xst" else: - _run_yosys(self.device, sources, build_name) + _run_yosys(self.device, sources, self.verilog_include_paths, build_name) isemode = "edif" ngdbuild_opt += "-p " + self.device -- 2.30.2