From 31b55b2a75cd439a00c5eeb3f246e4c2805137ed Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 8 May 2020 11:36:37 +1000 Subject: [PATCH] core: Improve core reset The icache would still spit out an instruction which could cause a 0x700 instead of a reset. Signed-off-by: Benjamin Herrenschmidt --- control.vhdl | 13 +++++++------ fetch2.vhdl | 1 + icache.vhdl | 2 +- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/control.vhdl b/control.vhdl index 064ff98..55f5649 100644 --- a/control.vhdl +++ b/control.vhdl @@ -159,6 +159,13 @@ begin v_int.outstanding := r_int.outstanding - 1; end if; + if rst = '1' then + v_int.state := IDLE; + v_int.outstanding := 0; + stall_tmp := '0'; + valid_tmp := '0'; + end if; + -- Handle debugger stop stopped_out <= '0'; if stop_mark_in = '1' and v_int.outstanding = 0 then @@ -228,12 +235,6 @@ begin cr_write_valid <= '0'; end if; - if rst = '1' then - v_int.state := IDLE; - v_int.outstanding := 0; - stall_tmp := '0'; - end if; - -- update outputs valid_out <= valid_tmp; stall_out <= stall_tmp; diff --git a/fetch2.vhdl b/fetch2.vhdl index 99f92ee..5474ca6 100644 --- a/fetch2.vhdl +++ b/fetch2.vhdl @@ -105,6 +105,7 @@ begin -- Clear stash on reset if rst = '1' then v_int.stash_valid := '0'; + v.valid := '0'; end if; -- Update registers diff --git a/icache.vhdl b/icache.vhdl index 343c73a..3eaf548 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -385,7 +385,7 @@ begin end loop; -- Generate the "hit" and "miss" signals for the synchronous blocks - req_is_hit <= i_in.req and is_hit and not flush_in; + req_is_hit <= i_in.req and is_hit and not flush_in and not rst; req_is_miss <= i_in.req and not is_hit and not flush_in; req_hit_way <= hit_way; -- 2.30.2