From 31baa4c0faa35d8970e6459971ac55218c120425 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 30 Apr 2020 18:30:23 +0100
Subject: [PATCH] add walk-through videos for LD/ST CompUnit

---
 3d_gpu/architecture/6600scoreboard.mdwn | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/3d_gpu/architecture/6600scoreboard.mdwn b/3d_gpu/architecture/6600scoreboard.mdwn
index 3371c4e95..0b75b2985 100644
--- a/3d_gpu/architecture/6600scoreboard.mdwn
+++ b/3d_gpu/architecture/6600scoreboard.mdwn
@@ -139,13 +139,19 @@ Discussions:
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-April/006167.html>
 * <https://groups.google.com/forum/#!topic/comp.arch/qeMsE7UxvlI>
 
+Walk-through Videos:
+
+* <https://www.youtube.com/watch?v=idDn1norNl0>
+* <https://www.youtube.com/watch?v=ipOe0cLOJWc>
+
 The Load/Store Computation Unit is a little more complex, involving
 three functions: LOAD, STORE, and LOAD-UPDATE.  The SR Latches create
 a forward-progressing Finite State Machine, with three possible paths:
 
 * LD Mode will activate Issue, GoRead1, GoAddr then finally GoWrite1
-* UPDATE Mode will activate Issue, GoRead1, GoAddr then GoWrite1 *and* 2.
+* LD-UPDATE Mode will *additionally* activate GoWrite2.
 * ST Mode will activate Issue, GoRead1, GoRead2, GoAddr then GoStore.
+  ST-UPDATE Mode will *additionally* activate GoWrite2.
 
 These signals will be allowed to activate when the correct "Req" lines
 are active.  Minor complications are involved (extra latches) that respond
-- 
2.30.2