From 31c6c5383af3f1d74225aa31365242bf84c594f5 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 7 Mar 2018 07:29:10 +0000
Subject: [PATCH]

---
 shakti/m_class/EINT.mdwn | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/shakti/m_class/EINT.mdwn b/shakti/m_class/EINT.mdwn
index fa3ca9b6f..8f7f7c3e8 100644
--- a/shakti/m_class/EINT.mdwn
+++ b/shakti/m_class/EINT.mdwn
@@ -1,7 +1,10 @@
 # EINT
 
+aka "PLIC"
+
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=14>
 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
   includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
   is a Watchdog Timer and others.
 * <https://opencores.org/project,simple_pic>
+* <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/plic/?at=master>
-- 
2.30.2