From 31ca7cbaa81e6a0f2425659797753e7c3e26b6ad Mon Sep 17 00:00:00 2001
From: Alan Lawrence <alan.lawrence@arm.com>
Date: Wed, 24 Jun 2015 16:26:38 +0000
Subject: [PATCH] [AArch64] Fix another ICE with -mgeneral-regs-only

gcc/:

	* config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
	Condition on TARGET_FLOAT.

gcc/testsuite/:

	* gcc.target/aarch64/mgeneral-regs_3.c: New.

From-SVN: r224910
---
 gcc/ChangeLog                                      |  5 +++++
 gcc/config/aarch64/aarch64.md                      |  2 +-
 gcc/testsuite/ChangeLog                            |  4 ++++
 gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c | 11 +++++++++++
 4 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf4f27c3d51..944e89c5fa5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
+
+	* config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
+	Condition on TARGET_FLOAT.
+
 2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
 
 	* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 934c8faf6d6..dbc4d1fbfee 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4117,7 +4117,7 @@
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
-  ""
+  "TARGET_FLOAT"
   "@
    <su_optab>cvtf\t%<GPF:s>0, %<s>1
    <su_optab>cvtf\t%<GPF:s>0, %<w1>1"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b9084a6e393..61045d38d2a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
+
+	* gcc.target/aarch64/mgeneral-regs_3.c: New.
+
 2015-06-24  Alan Lawrence  <alan.lawrence@arm.com>
 
 	* gcc.target/aarch64/mgeneral-regs_1.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
new file mode 100644
index 00000000000..f6b5fbae70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
@@ -0,0 +1,11 @@
+/* { dg-options "-mgeneral-regs-only -O2" } */
+
+extern void abort (void);
+
+int
+test (int i, ...)
+{
+  float f = (float) i; /* { dg-error "'-mgeneral-regs-only' is incompatible with floating-point code" } */
+  if (f != f) abort ();
+  return 2;
+}
-- 
2.30.2