From 31cd240d9a812d046cba0673cb01df857e9eaa02 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 20 Jun 2022 14:56:16 +0100 Subject: [PATCH] simplify paragraph, no need to "justify" statements. just make... statements --- svp64-primer/summary.tex | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index f9fd1eca6..1e14acf31 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -105,11 +105,12 @@ which can fit 1024 64-bit words \cite{riscv-v-spec}. The Cray-1 had overlaying the Vector Registers onto the Floating Point registers, similar to x86 "MMX". -Simple-V's "Vector" Registers are specifically designed to fit -on top of the Scalar (GPR, FPR) register files with \textbf{(byte-addressable access required?)}, which are extended from - the default of 32 (see PowerISA 3.2.1 General Purpose Registers and 4.2.1 Floating-Point Registers \textbf{[WHICH SPEC VERSION?]}), to 128 entries in the Libre-SOC implementation \textbf{[CAN WE REFER TO LIBRE-SOC?]}. This is a primary reason why Simple-V can be added -on top of an existing Scalar ISA, and \textit{in particular} why there -is no need to add Vector Registers or Vector instructions. +Simple-V's "Vector" Registers are specifically designed to fit on top of +the Scalar (GPR, FPR) register files, which are extended from the default +of 32, to 128 entries in the Libre-SOC implementation. This is a primary +reason why Simple-V can be added on top of an existing Scalar ISA, and +\textit{in particular} why there is no need to add Vector Registers or +Vector instructions. \begin{figure}[hb] \centering -- 2.30.2