From 31d118ffccd9935ec75075c83e84faa7246e22fe Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 10 Aug 2020 23:02:10 +0100 Subject: [PATCH] arch-arm: Fix SoftwareStep::debugExceptionReturnSS debugExceptionReturnSS is called on an ERET instruction to check for software step. The method was not using the SPSR.width and it was relying on the more generic ELIs32 to check the execution mode of the destination EL. This is not only an efficiency problem: the helper might not work when returning to EL0. In general it is not possible to understand if EL0 is using AArch32 or AArch64 if the current EL is not EL0 and EL1 is using AArch64. This is instead visible by inspecting the spsr.width during the execution of an ERET instruction Change-Id: Ibc5a43633d0020139f2c0e372959a3ab4880da6e Signed-off-by: Giacomo Travaglini Reviewed-by: Richard Cooper Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32634 Tested-by: kokoro --- src/arch/arm/insts/static_inst.cc | 2 +- src/arch/arm/self_debug.cc | 6 ++---- src/arch/arm/self_debug.hh | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 228149115..e55894cc8 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1194,7 +1194,7 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc); SoftwareStep *ss = sd->getSstep(); - new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest, new_cpsr.width); + new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest); return new_cpsr; } diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc index ef6ad6322..21ad84c37 100644 --- a/src/arch/arm/self_debug.cc +++ b/src/arch/arm/self_debug.cc @@ -643,7 +643,7 @@ WatchPoint::compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas, bool SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, - ExceptionLevel dest, bool aarch32) + ExceptionLevel dest) { bool SS_bit = false; bool enabled_src = false; @@ -652,9 +652,7 @@ SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, bool enabled_dst = false; bool secure = isSecureBelowEL3(tc) || dest == EL3; -// CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); -// if (cpsr.width) { - if (ELIs32(tc, dest)) { + if (spsr.width) { enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure, spsr.d == 1); } else { diff --git a/src/arch/arm/self_debug.hh b/src/arch/arm/self_debug.hh index 953a2dcda..7a96d4203 100644 --- a/src/arch/arm/self_debug.hh +++ b/src/arch/arm/self_debug.hh @@ -210,7 +210,7 @@ class SoftwareStep {} bool debugExceptionReturnSS(ThreadContext *tc, CPSR spsr, - ExceptionLevel dest, bool aarch32); + ExceptionLevel dest); bool advanceSS(ThreadContext *tc); inline void -- 2.30.2