From 31d1f5273eaaf72044b68d90c3d6242515fdd445 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 09:32:55 +0100 Subject: [PATCH] make carry output handling optional in common output stage --- src/soc/fu/common_output_stage.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 96de016b..cddf311f 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -32,9 +32,12 @@ class CommonOutputStage(PipeModBase): with m.Else(): comb += target.eq(o) - # Handle carry_out - comb += self.o.xer_ca.data.eq(self.i.xer_ca.data) - comb += self.o.xer_ca.ok.eq(op.output_carry) + # carry-out only if actually present in this input spec + # (note: MUL and DIV do not have it, but ALU and Logical do) + if hasattr(self.i.xer_ca): + # Handle carry_out + comb += self.o.xer_ca.data.eq(self.i.xer_ca.data) + comb += self.o.xer_ca.ok.eq(op.output_carry) # create condition register cr0 and sticky-overflow is_nzero = Signal(reset_less=True) -- 2.30.2