From 31dcc385686f963dd1c08de17b9838ff774b6224 Mon Sep 17 00:00:00 2001 From: Toma Tabacu Date: Fri, 3 Mar 2017 13:23:53 +0000 Subject: [PATCH] MIPS: Fix register mode checking for n64 in pr68273.c. gcc/testsuite/ * gcc.target/mips/pr68273.c (dg-final): Match SImode registers only for ilp32 targets and match DImode registers for lp64 targets. From-SVN: r245874 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/mips/pr68273.c | 7 +++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 508428460f3..a0e483078c1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-03-03 Toma Tabacu + + * gcc.target/mips/pr68273.c (dg-final): Match SImode registers only for + ilp32 targets and match DImode registers for lp64 targets. + 2017-03-03 Uros Bizjak * g++.dg/pr71624.C: Disable for x32. diff --git a/gcc/testsuite/gcc.target/mips/pr68273.c b/gcc/testsuite/gcc.target/mips/pr68273.c index cbe81e1e318..ce8ca930035 100644 --- a/gcc/testsuite/gcc.target/mips/pr68273.c +++ b/gcc/testsuite/gcc.target/mips/pr68273.c @@ -75,5 +75,8 @@ op (Node q) } -/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 5 \\\$5\\\)" 2 "expand" } } */ -/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 6 \\\$6\\\)" 1 "expand" } } */ +/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 5 \\\$5\\\)" 2 "expand" { target { ilp32 } } } } */ +/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:SI 6 \\\$6\\\)" 1 "expand" { target { ilp32 } } } } */ + +/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:DI 5 \\\$5\\\)" 2 "expand" { target { lp64 } } } } */ +/* { dg-final { scan-rtl-dump-times "\\\(set \\\(reg:DI 6 \\\$6\\\)" 1 "expand" { target { lp64 } } } } */ -- 2.30.2