From 31de10c4342bc5c21366d14a1266e942b95295a0 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 21 May 2020 18:51:52 -0400 Subject: [PATCH] pan/mdg: Disassemble out-of-order bits Optimization for texture instructions, allowing ALU and LD/ST within a single thread while a texture read is still in flight. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/panfrost/midgard/disassemble.c | 7 ++----- src/panfrost/midgard/midgard.h | 17 +++++++++++------ src/panfrost/midgard/midgard_compile.c | 4 ++-- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c index b4c9d772bb6..2b9fb0a2318 100644 --- a/src/panfrost/midgard/disassemble.c +++ b/src/panfrost/midgard/disassemble.c @@ -1441,11 +1441,8 @@ print_texture_word(FILE *fp, uint32_t *word, unsigned tabs, unsigned in_reg_base if (texture->last) fprintf(fp, ".last"); - if (texture->barrier_buffer) - fprintf(fp, ".barrier_buffer /* XXX */"); - - if (texture->barrier_shared) - fprintf(fp, ".barrier_shared /* XXX */"); + if (texture->out_of_order) + fprintf(fp, ".ooo%u", texture->out_of_order); /* Output modifiers are always interpreted floatly */ print_outmod(fp, texture->outmod, false); diff --git a/src/panfrost/midgard/midgard.h b/src/panfrost/midgard/midgard.h index 63f2fa2f586..4e7c80585d5 100644 --- a/src/panfrost/midgard/midgard.h +++ b/src/panfrost/midgard/midgard.h @@ -655,6 +655,9 @@ enum mali_sampler_type { MALI_SAMPLER_SIGNED = 0x3, /* isampler */ }; +#define MIDGARD_BARRIER_BUFFER (1 << 0) +#define MIDGARD_BARRIER_SHARED (1 << 1) + typedef struct __attribute__((__packed__)) { @@ -719,12 +722,14 @@ __attribute__((__packed__)) /* For barriers, control barriers are implied regardless, but these * bits also enable memory barriers of various types. For regular - * textures, these bits are not yet understood. */ - unsigned barrier_buffer : 1; - unsigned barrier_shared : 1; - unsigned barrier_stack : 1; - - unsigned unknown4 : 9; + * textures, these indicate how many bundles after this texture op may + * be executed in parallel with this op. We may execute only ALU and + * ld/st in parallel (not other textures), and obviously there cannot + * be any dependency (the blob appears to forbid even accessing other + * channels of a given texture register). */ + + unsigned out_of_order : 2; + unsigned unknown4 : 10; /* In immediate mode, each offset field is an immediate range [0, 7]. * diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 1841e0e0be2..e0d2f26a245 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -1436,8 +1436,8 @@ emit_control_barrier(compiler_context *ctx) .op = TEXTURE_OP_BARRIER, /* TODO: optimize */ - .barrier_buffer = 1, - .barrier_shared = 1 + .out_of_order = MIDGARD_BARRIER_BUFFER | + MIDGARD_BARRIER_SHARED , } }; -- 2.30.2